System-level performance evaluation of three-dimensional integrated circuits

Abstract

As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies.Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3 rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% -50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.

Architecture level TSV count minimization methodology for 3D tree-based FPGA

“…Considering the programmable interconnect overhead, FPGA is an ideal device that can benefit significantly by 3D integration, in which the circuits are integrated vertically by stacking multiple dies together and interconnected using TSVs [2]. Since FPGA is an interconnect dominated device, it is essential to minimize the TSV count because the TSVs consume more silicon area than horizontal interconnects.…”

“…The 3D integrated circuit (IC) technology has emerged as one of the most promising solutions for overcoming the challenges in interconnection and integration complexity in modern circuit designs [2]. TSV is the key enabling technology element for 3D integration, which is currently being actively evaluated as a potential solution to reduce the interconnect delay and increase the logic density in FPGA.…”

Thermal modeling and analysis of 3D multi-processor chips

“…This provides a modular ''snap-on'' functionality that could be included with developer systems, and omitted from consumer systems to keep the cost impact to a minimum, that will help on the profiling and introspection of the system. Rahman and Reif [8] evaluate system-level performance metrics in 3D integrated circuits. Other works explore cache implementations: [9,10] (where the authors present a delay and energy model, 3DCacti, to explore different 3D design options of partitioning a cache) and [11]; design of 3D arithmetic circuits: [12] (it is focused on a 3D microprocessor test vehicle and demonstrates the speed advantages derived from the 3D integration) and [13] (they show how a barrel shifter implemented in 3D exhibits a 9% reduction in latency with a simultaneous 8% reduction in energy).…”

Physical Design Issues in 3-D Integrated Technologies

“…The inherent advantage of 3-D integration is the drastic decrease in interconnect length, particularly the long global interconnects, which directly results in increased speed [3], [4], [5]. The interconnect power is also reduced as the capacitance of the wires decreases [6].…”