Systematic capacitance matching errors and corrective layout procedures

McNutt, M.J.; LeMarquis, S.; Dunkley, J.L.

doi:10.1109/4.284714

Cited by 120 publications

(67 citation statements)

References 13 publications

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“…The differential common centroid layout obviates wire crossing inevitable in the conventional crossconnected common centroid layout, eliminating the possibility of mismatch in wiring parasitics. Shielding by grounded metal-3 on top of the array blocks long-range fringe capacitance [58]. Dummy capacitors extending over a distance of at least 50 urn prevent uneven lithography at the boundaries from encroaching on the array.…”

Section: B Reconstruction Dia Converter (Dac)mentioning

confidence: 99%

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Pan

Segami

Choi

et al. 2000

Analog Circuit Design

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This paper discusses the impact of SFDR specification on the design of AID converter (ADC) in CMOS technology and describes the implementation of a prototype optimized for wide band SFDR performance for use in modem wireless base stations. The 6b-7b two-stage pipelined ADC using bootstrapping to linearize the sampling switch of on-chip track-hold achieves over 80 dB SFDR for signal frequencies up to 75 MHz at 50 MS/s without the need for trimming, calibration and dithering. INL is 1.3LSB, DNL is 0.8LSB. The 6b and 7b sub-ADC's are made efficient with averaging and folding. In 0.61J.m CMOS, the 16mm 2 ADC dissipates 850mW from 3.3V supply.

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Section: B Reconstruction Dia Converter (Dac)mentioning

confidence: 99%

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Pan

Segami

Choi

et al. 2000

Analog Circuit Design

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“…It can be argued that for a given resolution, the MBDAC requires larger sized unit capacitances than the BDAC to keep the noise voltage less than half the LSB. However, in modern standard CMOS technologies, the capacitor sizes are determined mainly by the matching requirements, which are stricter than those due to noise considerations [3,[13][14][15]. Moreover, the noise in the MBDAC degrades linearly with the increase in the number of conversion steps whereas the area savings grow exponentially.…”

Section: Performance Analysismentioning

confidence: 99%

“…In practice, however, this is not true and typically BDAC resolution is limited to eight to 10 bits. The large capacitance spread contributes to the high gradient mismatch [13][14][15]. The MBDAC can achieve this matching, as reflected in the second column in Table 1.…”

Section: B Effect Of Capacitor Mismatchesmentioning

confidence: 99%

Multi-step binary-weighted capacitive digital-to-analog converter architecture

Singh

Genov

Kotamraju

et al. 2008

2008 51st Midwest Symposium on Circuits and Systems

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Abstract-We present a capacitive digital-to-analog converter (DAC) architecture combining properties of the binary-weighted and serial charge-redistribution DACs to yield high integration density and high accuracy. The architecture provides the flexibility to trade area with conversion speed based on a set of area-speed-linearity constraints. We validate the architecture using a 10-bit two-step DAC example, simulated in a standard 0.35 m CMOS technology. The 10-bit DAC occupies 32 times less area than the conventional 10-bit binary-weighted DAC, has low INL, good matching, and high tolerance to parasitic capacitance.

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“…This is because each DNL step is defined by the random process variation of each unit capacitor value. A common centroid geometry layout technique can improve this capacitor matching for DNL, but it can not have an effect on random mismatch [13]. Naturally, increasing the capacitor size can directly improve the capacitor matching accuracy, but at the added cost of increased load capacitance.…”

Section: Introductionmentioning

confidence: 99%