Systematic Gate Stack Optimization to Maximize Mobility with HfSiON EOT Scaling

Quevedo‐Lopez, Manuel; Kirsch, P. D.; Krishnan, Sitaraman; Alshareef, Husam N.; Barnett, Joel; Harris, H. R.; Neugroschel, A.; Aguirre-Tostado, F. S.; Gnade, Bruce E.; Kim, M.; Wallace, Robert M.; Lee, B.

doi:10.1109/essder.2006.307651

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…This points to the importance of the remote scattering mechanisms where the sources of carrier scattering (e.g., charges, phonons, and roughness of the high-k layer) get closer to the channel with decreasing EOT. 30,31) In the case of Coulomb scattering by the fixed charges located at the dielectrics/semiconductor interface, the resultant mobility would not show such EOT dependence. EOT scaling may cause mobility degradation by the remote scattering mechanisms if a) scattering sources are present at or near the interface between the gate electrode and dielectric layer, or b) the EOT scaling of the high-k/interface layer/Si structure is the result of the scaling of the interface layer and the scattering sources are present in the high-k layer.…”

Section: Mosfet Characteristicsmentioning

confidence: 99%

Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Kouda

Suzuki

Kakushima

et al. 2012

Jpn. J. Appl. Phys.

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Stacked gate dielectrics composed of CeO2 and La2O3 were fabricated on Si substrates and their structures and electrical properties were investigated. Two types of stacked structures were compared: CeO2 grown on La2O3 (La2O3/CeO2) and La2O3 grown on CeO2 (CeO2/La2O3). The La2O3 and CeO2 layers were formed by atomic layer deposition (ALD) and chemical vapor deposition (CVD), respectively. The La2O3/CeO2 structure showed a larger equivalent oxide thickness (EOT) than the CeO2/La2O3 structure due to the silicate formation of the CeO2 layer in contact with Si. Metal–oxide–semiconductor field-effect transistors (MOSFETs) and capacitors constructed with the La2O3/CeO2 structure showed threshold and flat-band voltages close to the ideal ones. Effective channel mobilities for the MOSFETs were compared among three structures: single-layer La2O3, La2O3/CeO2, and CeO2/La2O3. EOT scaling was achieved without degrading the mobility of the CeO2/La2O3 structure, which reproduced previous results for the same structure formed by the electron-beam evaporation technique. The gate-leakage characteristics for the CVD/ALD samples were also investigated.

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Section: Mosfet Characteristicsmentioning

confidence: 99%

Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Kouda

Suzuki

Kakushima

et al. 2012

Jpn. J. Appl. Phys.

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“…Even if the interlayer lowers the effective k value of the film, it often gives better conditions for a transistor channel than those offered by a direct interface due to lower charge carrier scattering by the former. However, it must be paid for by an extra interface occurring between SiO x and the high-k material [4]. As the total physical thickness of the film is in the range of 5 nm or smaller, on this length scale the transition from SiO x to the high-k material can hardly be considered abrupt.…”

Section: Introductionmentioning

confidence: 99%

Charging Phenomena at the Interface Between High-k Dielectrics and SiOx Interlayers

Engström,

Raeissi,

Piscator

et al. 2010

JTIT

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The transition regions of GdSiO/SiOx and HfO2/SiOx interfaces have been studied with the high-k layers deposited on silicon substrates. The existence of transition regions was verified by medium energy ion scattering (MEIS) data and transmission electron microscopy (TEM). From measurements of thermally stimulated current (TSC), electron states were found in the transition region of the HfO2/SiOx structures, exhibiting instability attributed to the flexible structural molecular network expected to surround the trap volumes. The investigations were focused especially on whether the trap states belong to an agglomeration consisting of a single charge polarity or of a dipole constellation. We found that flat-band voltage shifts of MOS structures, that reach constant values for increasing oxide thickness, cannot be taken as unique evidence for the existence of dipole layers.

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“…After physical scaling, substantially reduced carrier mobilities were reported. 3,12) Thus, it is worth reanalyzing bias temperature instability to identify the dominant reliability concerns in MOSFETs with scaled high-k dielectrics. In this research, we carefully studied the charge-trapping characteristics of MOSFETs with various thicknesses of HfO 2 to find the dominant physical mechanism causing device instability.…”

Section: Introductionmentioning

confidence: 99%

Dominant Device Instability Mechanism in Scaled Metal–Oxide–Semiconductor Field-Effect Transistors with Hafnium Oxide Dielectric

Choi

Kim

Park³

et al. 2009

Jpn. J. Appl. Phys.

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The negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) of metal-oxide-semiconductor field-effect transistors (MOSFETs) with high dielectric constant (k ) gate dielectrics have been studied by varying the physical thickness of high-k dielectric. Both PBTI and NBTI were reduced with decrease in the high-k dielectric thickness, but NBTI reduction saturated in the thin highk region. Since residual NBTI is sufficiently large to cause device instability, NBTI is still a dominant reliability concern in scaled MOSFETs.

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Systematic Gate Stack Optimization to Maximize Mobility with HfSiON EOT Scaling

Cited by 3 publications

References 6 publications

Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Charging Phenomena at the Interface Between High-k Dielectrics and SiOx Interlayers

Dominant Device Instability Mechanism in Scaled Metal–Oxide–Semiconductor Field-Effect Transistors with Hafnium Oxide Dielectric

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Systematic Gate Stack Optimization to Maximize Mobility with HfSiON EOT Scaling

Cited by 3 publications

References 6 publications

Electrical Properties of CeO2/La2O3Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Electrical Properties of CeO2/La2O3Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Charging Phenomena at the Interface Between High-k Dielectrics and SiOx Interlayers

Dominant Device Instability Mechanism in Scaled Metal–Oxide–Semiconductor Field-Effect Transistors with Hafnium Oxide Dielectric

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Product

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About

Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition