Tagged communication and synchronization memory for multiprocessor‐on‐a‐chip

Iwane, Masahiko; Yamawaki, Akira; Tanaka, Makoto

doi:10.1002/scj.1014

Cited by 3 publications

(3 citation statements)

References 5 publications

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“…This includes mainly work on processor design (see e.g. [32,33,38,45]), verification of processor design (see e.g. [25,41]), timing analysis of computer-based systems (see e.g.…”

Section: Approachmentioning

confidence: 99%

Putting Instruction Sequences into Effect

Bergstra

2011

Preprint

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An attempt is made to define the concept of execution of an instruction sequence. It is found to be a special case of directly putting into effect of an instruction sequence. Directly putting into effect of an instruction sequences comprises interpretation as well as execution. Directly putting into effect is a special case of putting into effect with other special cases classified as indirectly putting into effect. Indirectly putting into effect an instruction sequence refers to a class of mechanical processes by default, which includes mechanisms making use of preparatory transformations and compilations of the entire instruction sequence or of significant parts thereof, where the transformations and compilations are themselves produced by means of putting yet other instruction sequences into effect. Returning to instruction sequence execution, its initial informal definition is: directly putting into effect an instruction sequence in such a way that it does not represent a form of interpretation, where a method of directly putting into effect is considered an interpretation if it represents an instance of the functionality produced by putting some other instruction sequence into effect (either directly or indirectly).

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“…This includes mainly work on processor design (see e.g. [32,33,38,45]), verification of processor design (see e.g. [25,41]), timing analysis of computer-based systems (see e.g.…”

Section: Approachmentioning

confidence: 99%

Putting Instruction Sequences into Effect

Bergstra

2011

Preprint

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“…The basic operations for the TSVM, like the TCSM [1], are the read, write, and reset operations using a TAG as the matching key.…”

Section: Operations Of Logical Tsvmmentioning

confidence: 99%

“…I-structure [2,12] and the write once variable [3] are a structured memory with the full/empty bit. The TCSM (Tagged communication and synchronization memory) [1] has a counter to perform a multicast efficiently. Entries in the TCSM are allocated dynamically since the TCSM consists of CAM (Content addressable memory).…”

Section: Introductionmentioning

confidence: 99%

Organization of shared memory with synchronization for multiprocessor-on-a-chip

Yamawaki

Iwane

Ninth International Conference on Parallel and Distributed Systems, 2002. Proceedings.

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The TSVM is a logical structured memory with a synchronization to improve a performance in a multi-threaded parallel processing. The physical TSVM is realized by the TSVM cache (TC) and a conventional memory in a Multiprocessor-on-a-chip (MOC) system. The L1 cache in a CPU consists of the TC, the General variable cache (GVC), and the instruction cache. The IYA (IY architecture) that is a new architecture divides a conventional data cache into the TC and GVC. The TC caches the shared variables with a synchronization, and the GVC caches other general variables. Regardless of a CPU core, a MOC with the IYA can utilize parallelisms from the instruction level and the statement level to the thread level systematically. To estimate the effect of the TC, preliminary experiments are performed on the multi-chip multiprocessor including the stand-alone TSVM. The result shows that the TSVM cache improves the performance.

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Hardware design in statement level parallel processing

Shimoo

Yamawaki

Iwane

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

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Tagged communication and synchronization memory for multiprocessor‐on‐a‐chip

Cited by 3 publications

References 5 publications

Putting Instruction Sequences into Effect

Putting Instruction Sequences into Effect

Organization of shared memory with synchronization for multiprocessor-on-a-chip

Hardware design in statement level parallel processing

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