Tail biting convolutional code decoder co-processor for high throughput System-on-Chip

Ramdani, Ahmad Zaky; Adiono, Trio

doi:10.1109/isocc.2015.7401708

Cited by 1 publication

(2 citation statements)

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“…The idea of reversed-trellis TBCC (RT-TBCC) algorithm is to find how tail-biting based Viterbi decoding process can be finished without iteration or at least has a fixed processing time [10]. Since the RT-TBCC algorithm is established from TBCC concept, it also utilizes the same initial and end states concept.…”

Section: Reversed-trellis Tbcc Algorithmmentioning

confidence: 99%

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Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE

Adiono

Ramdani

Putra

2018

IJECE

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Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixed-tail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.

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Section: Reversed-trellis Tbcc Algorithmmentioning

confidence: 99%

“…This article is extended version of papers entitled "A novel algorithm of tail biting convolutional code decoder for low cost hardware implementation" and "Tail biting convolutional code decoder coprocessor for high throughput System-on-Chip" that were published at ISPACS 2015 [4] and ISOCC 2015 [10] respectively.…”

Section: Acknowlegementsmentioning

confidence: 99%