Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes

Chang, Kuei-Chung; Shen, Jih-Sheng; Chen, Tien-Fu

doi:10.1145/1297666.1297678

Cited by 14 publications

(12 citation statements)

References 43 publications

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“…The router consists of packet process units (ingress and egress), an arbitration unit, and a switch fabric, and it provides a robust data transfer medium for the functional IP modules. Another solution for scalable architectures is to use circuit-switched NoC [6][7][8]. Chang [8] proposed a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for application-specific SoCs with few tens of cores.…”

Section: Related Workmentioning

confidence: 99%

“…Another solution for scalable architectures is to use circuit-switched NoC [6][7][8]. Chang [8] proposed a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for application-specific SoCs with few tens of cores. The structure of the crossroad switch is simple, which can be regarded as a NoC-lite router, and we can easily construct a low-power on-chip network with these switches by a system-level design methodology.…”

Section: Related Workmentioning

confidence: 99%

“…We simulated 10,000 packets generated by profiling the traffic characteristics of the MPEG-4 decoder. The experimental topology of the NoC is a 4 × 4 mesh network mapped by the approach in [8]. We used Orion [24], a power modeling tool, to develop bit energy models for the switches.…”

Section: Effects Of Error Detection In the Nocmentioning

confidence: 99%

See 2 more Smart Citations

Reliable network-on-chip design for multi-core system-on-chip

Chang

2009

J Supercomput

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Network-on-chip (NoC) architectures must deliver good latency-through put performance in the face of tight power and area budgets. However, in highperformance chip design, a significant design challenge is how to fulfill the requirements of circuit noise elimination, since the faults will slow down performance and dissipate much of the overall system power. This paper presents a simple coding scheme for reducing power dissipation, crosstalk noise, and crosstalk delay on the bus while simultaneously detecting errors at runtime. It uses a simple bus-invert encoding technique to reduce the prohibited transitions in terms of crosstalk noise and power dissipation. We also design a corresponding detector to detect errors at the input of the NoC routers. It can save energy by interrupting communications without storing and routing the packets when errors occur during transmissions. The experimental results for various multimedia applications show significant reduction in the number of patterns that are most likely to produce crosstalk errors. The results also show that it is attractive in terms of cost to apply the detecting logic to routers in the NoC with respect to the power consumption.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Reliable network-on-chip design for multi-core system-on-chip

Chang

2009

J Supercomput

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“…In spite of above advantages, NoC yet has the flaw that the communication infrastructures cost too much areas and power consumptions compared with the other components like process elements (PE) [17] [18]. The issue becomes more prominent in manycore approach.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

Wang

Wen

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

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The progress of manufacturing technology makes the integration of many cores on a single silica substrate possible, which is called chip multiprocessor (CMP). But how to design the fabric on chip is still in discussion. Based on the advantages of scalability, network on chip (NoC) is a promising solution to solve the on-chip interconnection problem. However, it is still a challenge when communications through wires dominate the performance. The network communications infrastructure (routing, adapters and wires, etc.) cost too much both in power consumption and die area. In this paper, we propose a novel on-chip structure with dynamic reconfiguration capability for I/O supported parallel application. Our motivation is to reduce the cost of chip areas greatly by dynamic reconfiguration of the network in NoC architecture under the conditions that I/O parallel applications can be supported and the performance can be optimized. In our design, I/O node will be obtained firstly and then the information of the spare processing elements (PE) near it. Finally, combined with the communication pattern of applications, wires will be reallocated and reconfigurated to create a virtual regionalized area. The experimental results show that we can get a certain level of optimization among chip area, communication efficiency and the performance of I/O supported parallel applications.

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“…In order to achieve a good cost-efficiency, the simulation of a new NoC at the early design stage is important [5] [7]. Therefore many NoC simulators have been built.…”

Section: Introductionmentioning

confidence: 99%

Object oriented network-on-chip modeling

Chang

Hsu

2010

2010 International Computer Symposium (ICS2010)

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The design of a NoC simulator can significantly affect its ability to explore various design space and simulation accuracy. It's not easy to achieve both wide-range design space exploration and detailed characterization of hardware components simultaneously. This paper presents a kind of NoC modeling in an object oriented flavor: object oriented NoC modeling ("OONoC" in brief). OONoC divides the NoC design space into many design blocks and each block into many abstraction levels. OONoC can extend the exploration space of NoC, study hardware characteristics, and significantly reduce the coding effort of a new NoC design.

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Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes

Cited by 14 publications

References 43 publications

Reliable network-on-chip design for multi-core system-on-chip

Reliable network-on-chip design for multi-core system-on-chip

Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

Object oriented network-on-chip modeling

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