TCAD-based characterization of logic cells: Power, performance, area, and variability

Karner, Hw.; Kernstock, C.; Stanojević, Z.; Baumgärtner, O.; Schanovsky, F.; Karner, M.; Helms, Domenik; Eilers, Reef; Metzdorf, Malte

doi:10.1109/vlsi-tsa.2017.7942453

Cited by 8 publications

(2 citation statements)

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“…Accounting for the transition rate and screening, the energy relaxation time and the physical mobility are accurately evaluated [16]. As compared to conventional TCAD framework, the physical level modeling has advantages that it captures the subband variations under strong confinement and considers multiple carrier scattering mechanisms, i.e., phonon scattering (acoustic, optical, and intervalley models), ionized impurity scattering, and surface roughness scattering directly, rather than empirical mobility models [17], [18]. Fig.…”

Section: Device Performance Analysis With Tcadmentioning

confidence: 99%

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Huo

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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This work presents a novel general compact model for 7-nm technology node devices like FinFETs as an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects. The general compact model exhibits efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control electrostatic discharge (ESD) power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for path-finding researches on 5-nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

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Section: Device Performance Analysis With Tcadmentioning

confidence: 99%

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Huo

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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“…Since these parameters have been widely used in the simulation of 4H-SiC IGBT, and the simulation results have been proved by experiments, these parameters and models have also been applied to this simulation. The models used in the simulation mainly include an energy band narrowing model (BGN), a parallel electric-field-dependent model (FLDMOB), a Fermi model, a concentration-dependent mobility model (CONMOB), and recombination models (Schockley-read-hall, AUGER) [30,31]. Figure 3 shows the forward I-V characteristic curves of C-IGBT and H-IGBT and the hole concentration distribution through the drift region.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss

Mao

Wang

Wu³

et al. 2019

Micromachines

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In this work, an insulated gate bipolar transistor (IGBT) is proposed that introduces a portion of the p-polySi/p-SiC heterojunction on the collector side to reduce the tail current during device turn-offs. By adjusting the doping concentration on both sides of the heterojunction, the turn-off loss is further reduced without sacrificing other characteristics of the device. The electrical characteristics of the device were simulated through the Silvaco ATLAS 2D simulation tool and compared with the traditional structure to verify the design idea. The simulation results show that, compared with the traditional structure, the turn-off loss of the proposed structure was reduced by 58.4%, the breakdown voltage increased by 13.3%, and the forward characteristics sacrificed 8.3%.

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Physical Design Implementation of SoC Module with Performance Optimization

Abhishek,

Kariyappa

2023

2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS)

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TCAD-based characterization of logic cells: Power, performance, area, and variability

Cited by 8 publications

References 0 publications

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss

Physical Design Implementation of SoC Module with Performance Optimization

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