TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices

Salamero, Christophe; Nolhier, Nicolas; Gendron, Amaury; Bafleur, Marise; Besse, Patrice; Zécri, M.

doi:10.1109/tdmr.2006.881483

Cited by 13 publications

(2 citation statements)

References 13 publications

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“…To discuss the I-V characteristics, ESD-induced latch-up effect, and the pulse performance, the direct current (DC), dynamic TLP-like (transmission line pulse-like), and TLP multiple-pulse simulations [18][19][20] have been used. Figure 2 shows the dynamic TLP-like simulation and TLP multiplepulse simulation circuit.…”

Section: Resultsmentioning

confidence: 99%

High holding voltage SCR for robust electrostatic discharge protection

Zhao

Qiao

et al. 2017

Chinese Phys. B

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A novel silicon controlled rectifier (SCR) with high holding voltage (V h ) for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high V h by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (I ESD ), the two SCRs are turned on at the same time to induce the first snapback with high V h (V h1 ). As the I ESD increases, the SCR2 will be turned off because of its low current gain. Therefore, the I ESD will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V h (V h2 ). The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized V h2 of 7.4 V with a maximum failure current (I t2 ) of 14.7 mA/µm is obtained by the simulation.

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Section: Resultsmentioning

confidence: 99%

High holding voltage SCR for robust electrostatic discharge protection

Zhao

Qiao

et al. 2017

Chinese Phys. B

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“…2D simulator models the electrical, thermal and optical characteristics of a wide variety of devices. Therefore, 2D simulation is commonly used in TCAD simulation to analyze the ESD characteristics of semiconductor devices [30,31,32]. In this paper 2D Silvaco TCAD is utilized to analyze the ESD behavior of the parasitic PNP bipolar transistor.…”

Section: Device Simulationmentioning

confidence: 99%

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Lai

Wang

et al. 2019

IEICE Electron. Express

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In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.

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