Technology CAD at IBM

Knepper, R.W.; Johnson, J. B.; Furkay, S.; Slinkman, J.; Tian, Xiubo; Buturla, E. M.; Young, Ralph W.; Fiorenza, G.; Logan, Robert K.; O'Brien, R. R.; Murthy, C. S.; Murley, P. C.; Peng, Jiawei; Tang, H.H.K.; Srinivasan, G. R.; Pelella, M.M.; Sunderland, D.A.; Mandelman, J.; Lieber, Derek; Farrell, Edward J.; Kurasic, M.

doi:10.1007/978-3-7091-9315-0_2

Cited by 5 publications

(2 citation statements)

References 19 publications

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“…9,17) The coupled system of device equations are solved in a self-consistent iterative scheme for both device and mixedmode (MM) simulations using FIELDAY. [18][19][20][21][22] The ET formulation is based on the first three moments of the Boltzmann transport equation (BTE). 23,24) The system of device equations solved in a fully-coupled manner are the Poisson equation, continuity of carrier concentrations (zeroth moment), conservation of carrier energy (second moment) with the constituent relations: the current density, carrier energy flux and the Wiedemann-Franz law for the electron gas.…”

Section: Device Structure and Simulation Frameworkmentioning

confidence: 99%

Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

Nayak

Bajaj²,

Konar³

et al. 2014

Jpn. J. Appl. Phys.

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In this paper, we present a fully-coupled and self-consistent continuum based three-dimensional numerical analysis to understand hot carrier and device self-heating effects for device-circuit co-optimization in Si gate-all-around nanowire FETs. We employ three-moment based energy transport formulations and two-dimensional quantum confinement effects to demonstrate negative differential conductivity in Si nanowire FETs and assess its impact on a CMOS inverter and three-stage ring oscillator. We show that strong two-dimensional quantum confinement yields volume inversion conditions in Si nanowire FETs and surround gate geometry enables better short-channel effect control. We find that hot carrier and self-heating effects can degrade ON-state current in Si nanowire FETs and severely limit the logic circuit performance due to the introduction of higher signal propagation delays.

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Section: Device Structure and Simulation Frameworkmentioning

confidence: 99%

Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

Nayak

Bajaj²,

Konar³

et al. 2014

Jpn. J. Appl. Phys.

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“…Energy band-gap (E G ) variation due to quantum size effects and lower lattice thermal conductivity values, with dirichlet thermal boundary conditions, are considered in the numerical study. The coupled system of device equations are solved in a self-consistent iterative scheme for both device and mixed-mode (MM) simulations [4]. The carrier mobility model parameters with quantum correction of inversion charge for Drift-Diffusion (DD) transport are calibrated with measured NWFET data [5].…”

Section: Device Structure and Simulation Frameworkmentioning

confidence: 99%

Negative differential conductivity in Gate-All-Around Si Nanowire FETs and its impact on Circuit Performance

Nayak¹,

Bajaj²,

Konar³

et al. 2013

Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials

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A fully-coupled continuum based 3-D numerical analysis is performed to understand the device-circuit co-optimization issues due to device self-heating and carrier heating effects in Si Gate All-Around (GAA) Nanowire Field Effect Transistors (NWFETs). Employing coupled 3-moment based Energy Transport (ET) formulations and Quantum Confinement (QC) effect; we report the evidence of Negative Differential Conductivity (NDC) in NWFETs and its effect on signal propagation delay in NWFET based CMOS inverter and 3-stage Ring Oscillator (RO) circuits.

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