Technology Mapping of FSM Oriented to LUT-Based FPGA

Kubica, Marcin; Kania, Dariusz

doi:10.3390/app10113926

Cited by 9 publications

(10 citation statements)

References 39 publications

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“…The problems of optimizing the characteristics of FSM circuits are discussed in many works, such as, for example, [30][31][32][33][34][35]. An analysis of these and many other works allowed us to draw the following conclusion.…”

Section: Related Workmentioning

confidence: 99%

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Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible.

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Section: Related Workmentioning

confidence: 99%

“…The table of the CM is used to derive SBF (24). In the discussed case, SBF (33) represents the circuit of CPO1 and SBF (34) represents the block CM:…”

Section: Cs Pc(cs) St Fc(st)mentioning

confidence: 99%

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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“…Researchers have devoted significant attention to the optimization of Finite State Machine (FSM) implementations regarding area, speed, or power consumption over decades [1][2][3][4][5][6][7][8]. Current Field Programmable Gate Array (FPGA) devices include Embedded Memory Blocks (EMBs), which allow, among other elements, the implementation of ROM memory.…”

Section: Introductionmentioning

confidence: 99%

A New Approach for Implementing Finite State Machines with Input Multiplexing

Garcia-Vargas,

Senhadji-Navarro

2023

Electronics

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The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. The aim of the proposed approach is to obtain further reductions in the use of Embedded Memory Blocks (EMBs). Unlike previous works, the proposed approach reduces the depth of the ROM by grouping states before simplifying the input selectors of the FSMIM. For this purpose, a new strategy for grouping states is proposed, and its optimality is proven. In addition, a new variant of the Minimum Maximal k-Partial Matching (MMKPM) problem and its corresponding Integer Linear Programming (ILP) formulation are proposed for simplifying input selectors. The proposed approach requires a significantly smaller number of EMBs than the approaches proposed previously.

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“…In digital design, the implementation of Finite State Machines (FSMs) has received attention from researchers for decades [1][2][3][4][5][6][7][8]. Optimizing FSM implementations in terms of area, speed or power consumption is essential to meet the design constraints demanded by applications.…”

Section: Introductionmentioning

confidence: 99%

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

García-Vargas

Senhadji-Navarro

2022

Des Autom Embed Syst

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Finite State Machines with Input Multiplexing (FSMIMs) were proposed in previous work as a technique for efficient mapping Finite State Machines (FSMs) into ROM memory. In this paper, we present new contributions to the optimization process involved in the implementation of FSMIMs in Field Programmable Gate Array (FPGA) devices. This process consists of two stages: (1) the simplification of the bank of input selectors of the FSMIM, and (2) the reduction of the depth of the ROM. This has a significant impact both on the number of used Look-Up Tables (LUTs) and on the number of the Embedded Memory Blocks (EMBs) required by the ROM. For the first stage, we present two approaches to optimize FSMIM implementations based on the Minimum Maximal k-Partial Matching (MMKPM) problem: one of them applies the greedy algorithm for the MMKPM problem, and the other based on a new multiobjetive variant of the MMKPM and its corresponding Integer Linear Programing formulation. We also propose a modification of the second stage, in which the characteristics of EMBs are taken into account to improve implementation results. The new optimization process significantly reduces the number of used FPGA resources with respect to the previous one. In addition, the proposed approaches achieve an adequate trade-off between the usage of EMBs and LUTs with respect to conventional FSM implementations based on ROM and to those based on LUT.

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Technology Mapping of FSM Oriented to LUT-Based FPGA

Cited by 9 publications

References 39 publications

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

A New Approach for Implementing Finite State Machines with Input Multiplexing

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

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