Temperature-aware routing in 3D ICs

Abstract

Three-dimensional integrated circuits (3D ICs)

Temperature-Aware Design and Management for 3D Multi-Core Architectures

“…Temperature-aware routing of lateral thermal wires and vertical thermal vias has been proposed [84]. This work adds the utilization of lateral thermal wires, which are signal non-carrying wires thus have no electric functionality.…”

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

“…These TSVs are typically called thermal or dummy vias [18] to emphasize the objective of conveying heat rather than providing signal communication for circuits located on different physical planes. Thermal wires can also be employed to transfer heat [56]. Thermal wires correspond to those horizontal wires that connect regions with different thermal via densities through thermal interplane vias.…”

“…In addition to the benefits that the added thermal vias produce, thermal wires can also be utilized to enhance the heat transfer process. These thermal wires are treated as routing channels wherever there are available tracks [56].…”

Co-optimization of TSV assignment and micro-channel placement for 3D-ICs

“…investigated: Post Placement [1][2] [3] and In-placement [4]. In Post Placement approaches, cells are firstly placed in the 3D-IC.…”

“…This determines the whitespace distribution capable of supporting TSVs. These potential TSV locations are then allocated to the interlayer nets such that the total wirelength is minimized [1][2] [3]. In-placement approaches perform simultaneous optimization of cell placement, TSV placement and interlayer net to TSV assignment during the 3D-IC placement process itself.…”