Temperature dependence of drain-induced barrierlowering in deep submicrometre MOSFETs

Fikry, W.; Ghibaudo, G.; Dutoit, M.

doi:10.1049/el:19940577

Cited by 23 publications

(10 citation statements)

References 5 publications

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“…Therefore, the DTBL effect is not impacting flMR extraction for short channel devices. Electri cal extraction was performed, using a velocity saturation-based model for drain current in saturation [24][25]. Figure 4 shows extracted Vsats variation with B for the 10 flmxO.5 flm device at 270 K. A parabolic behavior was found.…”

Section: It Measurement and Resultsmentioning

confidence: 99%

Magnetoresistance mobility extraction in the saturation regime of short channel MOS devices

Narasimhamoorthy

Ghibaudo

Mouis

et al. 2012

2012 International Semiconductor Conference Dresden-Grenoble (ISCDG)

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The effect of magnetic field in the saturation regime of sub �m MOSFETs is being reported here for the first time. The study was based on bulk MOSFETs featuring a high-Klmetal gate with an equivalent oxide thickness of 2.4 nm. Channel length ranged from 1 �m down to 50 nm, while width was kept constant at 10 �m. It is found that it is possible to extract a magnetoresis tance mobility �MR even in the saturation regime of operation and in turn study the observed �MR against channel length, tem perature, drain voltage and gate voltage. For these sub-micron devices, electron transport is influenced by the high electric field that exists in the channel and velocity saturation, velocity over shoot and even quasi-ballistic effects could playa role for the shortest channel lengths Here, the observed �MR behavior is well interpreted using velocity saturation and overshoot effects.

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Section: It Measurement and Resultsmentioning

confidence: 99%

Magnetoresistance mobility extraction in the saturation regime of short channel MOS devices

Narasimhamoorthy

Ghibaudo

Mouis

et al. 2012

2012 International Semiconductor Conference Dresden-Grenoble (ISCDG)

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“…The DIBL results in a linear increase with drain voltage of the threshold voltage such that Vt=VtO-AV d [57,58]. As the drain current depends essentially on the gate voltage drive from weak to strong inversion, it is easy to show that in the saturation region the output conductance to gate transconductance ratio gives access to the DIBL parameter as [59]: (16). This method has been applied to deep submicron N MOS transistors with gate oxide thickness of 55A and channel lengths ranging between 0.1 and 2~m.…”

Section: Drain Induced Barrier Lowering (Dlbl)mentioning

confidence: 98%

“…The values of A, have been extracted using Eq. 16 from the minimum of the gdlgm(VaJ characteristics for all the geometries and temperatures [59]. Figure 18 (a) shows the evolution of the DIBL coefficient as a function of channel length for various temperatures between 50K and 300K.…”

Section: Drain Induced Barrier Lowering (Dlbl)mentioning

confidence: 99%

“…For this reason, the temperature dependence of the DIBL effect is a major issue to be addressed for application at cryogenic conditions. The DIBL effect has been extensively studied as a function of temperature on deep submicron MOS devices between room and near liquid helium temperatures [59]. To this end, a specific method for the extraction of the DIBL coefficient has been used.…”

Section: Drain Induced Barrier Lowering (Dlbl)mentioning

confidence: 99%

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Device Physics and Electrical Performance of Bulk Silicon Mosfets

Ghibaudo¹

2001

Device and Circuit Cryogenic Operation for Low Temperature Electronics

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“…The study in [44] shows data supporting the notion that the DIBL coefficient is temperature sensitive, particularly for shorter channel lengths. An insensitivity to temperature of DIBL as a percentage of subthreshold current is shown in [54] for deep submicron MOSFETs between -223°C and 27°C and in [52] for 0.25µm PMOS transistors between -50°C and 125°C.…”

Section: )mentioning

confidence: 99%

The Role of Temperature in Testing Deep Submicron CMOS ASICs

Long¹

2000

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Title: The Role Of Temperature In Testing Deep Submicron CMOS ASICs.Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25µm and 0.18µm CMOS ASICs fabricated by LSI Logic. An IC's performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC's constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.c

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Temperature dependence of drain-induced barrierlowering in deep submicrometre MOSFETs

Cited by 23 publications

References 5 publications

Magnetoresistance mobility extraction in the saturation regime of short channel MOS devices

Magnetoresistance mobility extraction in the saturation regime of short channel MOS devices

Device Physics and Electrical Performance of Bulk Silicon Mosfets

The Role of Temperature in Testing Deep Submicron CMOS ASICs

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