This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOSspecific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

The effect of magnetic field in the saturation regime of sub �m MOSFETs is being reported here for the first time. The study was based on bulk MOSFETs featuring a high-Klmetal gate with an equivalent oxide thickness of 2.4 nm. Channel length ranged from 1 �m down to 50 nm, while width was kept constant at 10 �m. It is found that it is possible to extract a magnetoresis tance mobility �MR even in the saturation regime of operation and in turn study the observed �MR against channel length, tem perature, drain voltage and gate voltage. For these sub-micron devices, electron transport is influenced by the high electric field that exists in the channel and velocity saturation, velocity over shoot and even quasi-ballistic effects could playa role for the shortest channel lengths Here, the observed �MR behavior is well interpreted using velocity saturation and overshoot effects.

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