Temperature dependence of neutron-induced soft errors in SRAMs

Bagatin, M.; Gerardin, Simone; Paccagnella, A.; Gorini, G.; Frost, Christopher

doi:10.1016/j.microrel.2011.08.011

Cited by 24 publications

(6 citation statements)

References 24 publications

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“…Temperature variations are crucial, especially for space, military, nuclear, and avionics applications, i.e., applications that are usually affected by soft errors. At the experimental level, several works investigate the impact of temperature on device sensitivity, such as in [8][9][10], where the high temperature effect was studied when irradiating SRAMs with protons. However, very few of these studies involved irradiating SRAMs with neutrons.…”

Section: State-of-the-art Methodsmentioning

confidence: 99%

Soft errors in commercial off-the-shelf static random access memories

Dilillo

Bosser

Saigné

et al. 2016

Semicond. Sci. Technol.

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This article reviews state-of-the-art techniques for the evaluation of the effect of radiation on static random access memory (SRAM). We detailed irradiation test techniques and results from irradiation experiments with several types of particles. Two commercial SRAMs, in 90 and 65 nm technology nodes, were considered as case studies. Besides the basic static and dynamic test modes, advanced stimuli for the irradiation tests were introduced, as well as statistical postprocessing techniques allowing for deeper analysis of the correlations between bit-flip crosssections and design/architectural characteristics of the memory device. Further insight is provided on the response of irradiated stacked layer devices and on the use of characterized SRAM devices as particle detectors.

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Section: State-of-the-art Methodsmentioning

confidence: 99%

Soft errors in commercial off-the-shelf static random access memories

Dilillo

Bosser

Saigné

et al. 2016

Semicond. Sci. Technol.

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“…With the increasing proliferation of battery-powered systems (e.g., in transport) and the higher demand of more functionality in the hardware platform, the new scenario demands more power-efficient computing platforms also for safety-critical applications, where this hardware is centralized in inherently more power hungry and complex platforms (e.g., heterogeneous and multicore SoCs). Therefore, the focus of the research is on how those low-power techniques may impact the functional safety at the system level (e.g., not in the microelectronics reliability, as other works correlated power and temperature with soft-errors rates [18]). From this overall safety perspective, this carries the following challenges:…”

Section: Impact On Safetymentioning

confidence: 99%

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Fakih

Grüttner

Schreiner

et al. 2019

JLPEA

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With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.

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“…Moreover, in the case of circuits operating at sub-V T level, some reliability issues have taken on even more importance in terms of performance, such as process variations, changes in temperature, and soft errors. 21 This subsection describes the different reliability scenarios considered in the analysis of the gain-cell eDRAM's behavior.…”

Section: Reliability Concerns For Studying Edram Cell Suitability At mentioning

confidence: 99%

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

Amat¹,

Calomarde²,

Canal³

et al. 2018

Journal of Low Power Electronics

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Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to achieve the maximum cell performance (i.e., retention time, access time, and energy consumption) suitable for the sub-V T operating level. In this work, we show that asymmetrically resizing the memory cell (i.e., the channel length of the write access transistor and the width of the rest of the devices) results in a 3.5× increase in retention time when compared to the nominal case while reducing area, as well. In terms of reliability (e.g., variability and soft errors), the resizing also improves the cell robustness (50% and 1.9×, respectively) when the cells are operated at sub-V T level.

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Temperature dependence of neutron-induced soft errors in SRAMs

Cited by 24 publications

References 24 publications

Soft errors in commercial off-the-shelf static random access memories

Soft errors in commercial off-the-shelf static random access memories

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs

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Temperature dependence of neutron-induced soft errors in SRAMs

Cited by 24 publications

References 24 publications

Soft errors in commercial off-the-shelf static random access memories

Soft errors in commercial off-the-shelf static random access memories

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Optimization of FinFET-Based Gain Cells for Low Power Sub-VT Embedded DRAMs

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Optimization of FinFET-Based Gain Cells for Low Power Sub-V_T Embedded DRAMs