Temperature Effect on Heavy-Ion-Induced Single-Event Transient Propagation in CMOS Bulk 0.18 $\mu$m Inverter Chain

Truyen, D.; Boch, J.; Sagnes, B.; Vaillé, J.-R.; Renaud, Nicolas; Leduc, E.; Briet, M.; Heng, Chun-Huat; Mouton, S.; Saigné, Frédéric

doi:10.1109/tns.2008.2000851

Cited by 15 publications

(8 citation statements)

References 18 publications

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“…The time delay of the current pulse defined at 10% of the maximum is however increased with temperature. Similar results have been found in previous works for a temperature up to 418K [7], [12]. This behavior can be explained for the maximum current amplitude I, by the average of the electron mobility µ [13]:…”

Section: Ii1-simulation Of a Single Soi Nmos Transistorsupporting

confidence: 90%

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Boufouss

Pulido

Flandre

2010

Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixedmode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.

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Section: Ii1-simulation Of a Single Soi Nmos Transistorsupporting

confidence: 90%

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Boufouss

Pulido

Flandre

2010

Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)

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show abstract

“…b Block diagram of 90-300 K DUT temperature measurement and control system temperature. As reported previously [3,[7][8][9][10][11], the transient current peak value decreases as temperature increases, as the pulse width increases with temperature rising. Singleevent error rates for microcircuits are a strong function of SET pulse width [16,17].…”

Section: Temperature Influence On Setsupporting

confidence: 80%

“…Truyen et al [6] also studied the temperature dependence of a SEU in an ATMEL 0.18-lm SRAM memory cell, but the results indicate that the SEU sensitivity depends weakly on temperature with a parabolic shape. Recently, both heavy ion experiments and technology computer-aided design (TCAD) simulations show that SET pulse width increases significantly with temperature [7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Experimental study of temperature dependence of single-event upset in SRAMs

et al. 2016

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We report on the temperature dependence of single-event upsets in the 215-353 K range in a 4M commercial SRAM manufactured in a 0.15-lm CMOS process, utilizing thin film transistors. The experimental results show that temperature influences the SEU cross section on the rising portion of the cross-sectional curve (such as the chlorine ion incident). SEU cross section increases 257 % when the temperature increases from 215 to 353 K. One of the possible reasons for this is that it is due to the variation in upset voltage induced by changing temperature.

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“…Many SET studies have thus been performed using TCAD simulations [55] [56]. However, complex ICs such as wide logic gate circuits cannot be considered since finite element methodologies used by TCAD tools are time consuming.…”

Section: B Set Generation: Charge Collection Mechanisms In Electronimentioning

confidence: 99%

Modeling Single Event Transients in Advanced Devices and ICs

Artola

Gaillardin

Hubert

et al. 2015

IEEE Trans. Nucl. Sci.

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The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.

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Temperature Effect on Heavy-Ion-Induced Single-Event Transient Propagation in CMOS Bulk 0.18 $\mu$m Inverter Chain

Cited by 15 publications

References 18 publications

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Experimental study of temperature dependence of single-event upset in SRAMs

Modeling Single Event Transients in Advanced Devices and ICs

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