Temperature effects on Ge condensation by thermal oxidation of SiGe-on-insulator structures

Sugiyama, N.; Tezuka, T.; Mizuno, Tomohisa; Suzuki, Masatoshi; Ishikawa, Yukari; Shibata, Noriyoshi; Takagi, Shinichi

doi:10.1063/1.1649812

Cited by 86 publications

(51 citation statements)

References 8 publications

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“…The strained Si on insulator (sSOI) structure is attractive for realization of high-performance complimentary metal-oxide-semiconductor field effect transistors (CMOS) due to the strain-enhanced carrier mobility and reduction of parasitic capacitance [1][2][3]. High temperature oxidation (N1100°C) process is usually used to induce Ge condensation process of SiGe/SOI structures, which is employed to fabricate strained Si on SGOI [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Comprehensive study of low temperature (< 1000 °C) oxidation process in SiGe/SOI structures

et al. 2008

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Section: Introductionmentioning

confidence: 99%

Comprehensive study of low temperature (< 1000 °C) oxidation process in SiGe/SOI structures

et al. 2008

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“…It is found that there is a clear difference in the strain relaxation behavior between the two oxidation temperature recipe and that the oxidation at higher temperatures in the recipe A can lead to higher strain at a given Ge fraction, higher maximum strain values and higher Ge fraction at the maximum strain point, all of which are favorable in terms of the enhancement of the hole mobility in SGOI. This oxidation temperature dependence of the strain relaxation can be explained by the diffusion of Ge atoms segregated at SiO 2 /SiGe interfaces toward the SiGe/SOI substrates [12,13]. It has been reported that the activation energy of the Ge diffusion in SiGe layers, 5.8eV [14], is much higher than that of the oxygen diffusion in SiO 2 , 1.17eV [15], which determines the velocity of the movement of the SiO 2 /SiGe interface and the resulting generation rate of segregated Ge atoms at the interface during the Ge condensation.…”

Section: Ecs Transactions 33 (6) 501-509 (2010)mentioning

confidence: 99%

“…At higher oxidation temperature, the diffusion of Ge atoms surpasses the pile up of Ge atoms at the MOS interfaces due to the segregation associated with the oxidation of SiGe, resulting in the much smaller Ge concentration gradient and the flatter Ge fraction profile in SGOI. A lower temperature, on the other hand, the Ge profile becomes more abrupt, leading to the generation of dislocations and defects [12], which can cause the strain ECS Transactions, 33 (6) 501-509 (2010) relaxation. From this viewpoint, the oxidation temperature of as high as possible is better in maintaining the higher strain in SGOI.…”

Section: Ecs Transactions 33 (6) 501-509 (2010)mentioning

confidence: 99%

Critical Factors for Enhancement of Compressive Strain in SGOI Layers Fabricated by Ge Condensation Technique

et al. 2010

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SGOI layers with high compressive strain and high Ge content are promising channel materials for high current drive pMOSFETs under future technology nodes. In order to clarify the way of maximizing strain in SiGe-On-Insulator (SGOI) structures with high Ge fraction fabricated by th Ge condensation technique, we have examined the strain relaxation behaviors of the SGOI layers during the condensation process. The relationship among compressive strain in SGOI, the oxidation recipe and the substrate structures before oxidation has been quantitatively evaluated. With increasing the Ge fraction, the compressive strain in the SGOI layers linearly increases in lower Ge contents and rapidly decreases after it reaches peak values. It is found that the higher oxidation temperature and the Ge content in the SiGe epitaxial layers before oxidation are influential factors in mitigating the strain relaxation, in addition to the use of the strained Si-OnInsulator (sSOI) substrates As a result of optimizing these structural parameters, we have successfully obtained SGOI with 2.5% compressive strain under the Ge content of 0.86.

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“…In order to improve the substrate crystal quality, the Si 0.7 Ge 0.3 substrates were prepared by the Ge condensation method using a 150 nm thick Si 0.85 Ge 0.15 film deposited on an 8-inch n-type Silicon-on-Insulator (SOI) wafer. The details of the fabrication process have been reported elsewhere [7]. Arsenic was implanted into all samples at 30 keV with a dose of 2×10 15 cm 2 and then activated at 1000°C for 5 s. After surface cleaning using H 2 SO 4 :H 2 O 2 =4:1 for 3 min followed by a 1 min dip in a…”

mentioning

confidence: 99%

Erbium germanosilicide Ohmic contacts on Si1−x Ge x (x=0–0.3) substrates

Xiang

2011

Sci. China Phys. Mech. Astron.

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We have studied erbium germanosilicide (ErSiGe) Ohmic contacts on n-type Si 1x Ge x substrates with differing Ge concentrations (0x0.3). Thin layers of Ti (20 nm)/Er (20 nm) were deposited on Si 1x Ge x substrates and then post-annealed at 600°C for 60 s to form a stable ErSiGe film. The structures of the ErSiGe films and ErSiGe/Si 1x Ge x interfaces were characterized by Transmission Electron Microscopy measurements (TEM). The TEM images showed that the thicknesses of ErSiGe films and the Si 1x Ge x substrates were about 60 and 50 nm, respectively. The ErSiGe/Si 1x Ge x structure had a smooth interface. Moreover, no agglomeration or Ge segregation was observed. The contact resistivity of the ErSiGe/Si 1x Ge x structures was measured by the specially designed four-terminal Kelvin structures. When the Ge concentration of Si 1x Ge x substrates increased from 10% to 30%, the specific contact resistivity ( c ) slightly decreased from 9.0×10 7 ·cm 2 to 7.4×10 7 ·cm 2 , indicating that the Ge concentration is not the main effect on the  c of the ErSiGe/Si 1x Ge x Ohmic contacts. specific contact resistivity, erbium germanosilicide, Ohmic contact, Ge concentration PACS: 73.40.Cg, 81.05.Bx, 73.40.NsAs the critical feature size of semiconductor devices decreases, the junction depth of the source/drain and size of other associated device features also decreases causing an increase in the parasitic resistance. The parasitic resistance component does not scale with device dimensions and thereby contributes to an appreciable fraction of the total resistance, resulting in significant performance and reliability degradation of the integrated circuits. According to the International Technology Roadmap for Semiconductors (ITRS), the contact resistivity has to be below 1×10 7 ·cm 2 for CMOS technology beyond 65 nm. In order to reduce the contact resistivity, rare earth silicides (especially erbium) have drawn a lot of attention because of their advantages: good thermal stability, low Schottky barrier on Si substrates, and their compatibility with Si CMOS technologies [1-3]. Recently, silicon germanium has been used in the source/drain region of high speed CMOS to enhance mobility by inducing channel strain [4]. In order to decrease the contact resistance between the metal electrodes and source/ drain region, the structural and electrical properties of many kinds of germanosilicides on Si 1x Ge x substrates have been investigated [5,6]. In this paper, we study the contact resistivity of ErSiGe/Si 1x Ge x (x=0-0.3) Ohmic contacts.Si 1x Ge x substrates with 10% and 30% Ge concentrations were used for this study. For the 10% Ge concentration substrates, a 50 nm thick Si 0.9 Ge 0.1 epitaxial film was grown on an 8-inch n-Si (100) wafer using high vacuum chemical vapor deposition. In order to improve the substrate crystal quality, the Si 0.7 Ge 0.3 substrates were prepared by the Ge condensation method using a 150 nm thick Si 0.85 Ge 0.15 film deposited on an 8-inch n-type Silicon-on-Insulator (SOI) wafer. The detai...

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Temperature effects on Ge condensation by thermal oxidation of SiGe-on-insulator structures

Cited by 86 publications

References 8 publications

Comprehensive study of low temperature (< 1000 °C) oxidation process in SiGe/SOI structures

Comprehensive study of low temperature (< 1000 °C) oxidation process in SiGe/SOI structures

Critical Factors for Enhancement of Compressive Strain in SGOI Layers Fabricated by Ge Condensation Technique

Erbium germanosilicide Ohmic contacts on Si1−x Ge x (x=0–0.3) substrates

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