Comprehensive study of low temperature (&lt; 1000 °C) oxidation process in SiGe/SOI structures

Tanaka, Masanori; Ohka, Tatsuo; Sadoh, Taizoh; Miyao, Masanobu

doi:10.1016/j.tsf.2008.08.025

Cited by 6 publications

(3 citation statements)

References 13 publications

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“…Therefore, for SiGe material realize a high-quality IL between the high-k gate dielectric and SiGe channel by using the passivation process. Among the present passivation methods, such as thermal oxidation [8][9][10][11] and plasma treatment (O 2 , N 2 or NH 3 ) [12][13][14][15][16], in-situ ozone oxidation is considered the most promising strategy [17][18][19][20]. This is because it not only achieves a high-quality IL with an in-situ low thermal budget, but it is also more suitable for advanced three-dimensional devices, such as fin field effect transistors (FinFETs) or gate-all-around field effect transistors, due to its isotropic characterization [19,21].…”

Section: Introductionmentioning

confidence: 99%

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Chen¹,

Li²,

Yao³

et al. 2022

Semicond. Sci. Technol.

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In this paper, the optimization of SiGe interface property for SiGe channel FinFET transistor is explored in detail. First, an optimal low-temperature ozone oxidation at 300 ℃ for 30 min was confirmed based on the Al2O3/Si0.7Ge0.3 MOS capacitors. This is because that a higher oxidation temperature and a longer oxidation time could suppress the formation of GeOX in the interface layer (IL), and significantly improve interface state density (Dit). Moreover, compared with Al2O3 sample, HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface property because the GeOX in the IL is more likely to diffuse into HfO2 layer. To further optimize the Dit and CET of Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersions characteristics and Dit have been improved significantly since the thin Al2O3 layer prevents the diffusion of GeOX to HfO2 layer and controls the growth of GeOX. Therefore, a high quality Si0.7Ge0.3 interface property optimization technology is realized by development of a low-temperature ozone oxidation (300 ℃, 30 min) combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 is obtained. The above result proves that these newly developed interface property optimization scheme is a practical technology for high mobility SiGe FinFET.

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Section: Introductionmentioning

confidence: 99%

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Chen¹,

Li²,

Yao³

et al. 2022

Semicond. Sci. Technol.

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“…The main disadvantage of this method is the trade-off between the interface quality and the scalability of equivalent oxide thickness (EOT). Oxides on SiGe have also been extensively investigated as passivation layers between high-k and SiGe, which are formed by oxidizing SiGe surface via various approaches, such as thermal O 2 oxidation [9][10][11][12][13][14], O plasma [15,16], and ozone [17,18]. Conventional thermal O 2 oxidation are performed at high pressures and temperatures resulting in thick oxides and Ge-rich layers beneath the oxides, which are unsuitable as the passivation layers between high-k and SiGe.…”

Section: Introductionmentioning

confidence: 99%

Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces

Xiang

Zhou

et al. 2020

Semicond. Sci. Technol.

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High-k/SiGe interface control for low interface state density (D it ) is one of the most critical issues for realizing SiGe-based MOSFETs. Among various SiGe MOS interlayers (ILs), oxide IL passivation performed by low-temperature ozone oxidation is one of the most promising methods. In this study, we have examined the interfacial chemical structures and the electrical properties of the Al 2 O 3 /IL/SiGe gate stacks fabricated under various ozone oxidation conditions. It is experimentally found that D it values vary with two factors, one is the SiO x thickness and the other is the ratio of Si 4+ component in SiO x . The increase in the SiO x thickness causes more Ge atoms to accumulate at the IL/SiGe interface, which means more Ge dangling bonds at the interface and higher D it in the band gap. Conversely, the increase in the ratio of Si 4+ component in SiO x leads to a decrease in D it . Based on the perturbation theory of quantum mechanisms, this phenomenon may be explained by the remote coulomb potential perturbation arising from high-oxidation-state Si atoms.

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“…[8][9][10][11][12] The main disadvantage of this approach is the parasitic Si cap channel and the reduced scalability of the equivalent oxide thickness (EOT) because SiO 2 has a lower dielectric constant than highk materials. SiGe interfaces formed by thermal oxidation have also been investigated, [13][14][15][16] however, conventional high-temperature oxidation processes have been shown to result in an undesired relaxation of strained SiGe layer, which would significantly degrade the electrical performances of the MOS devices such as interface state density (D it ) and breakdown field (E break ). To solve these problems, many lowtemperature oxidation processes for interlayer (IL) formation have been explored, such as O plasma 17,18 and ozone oxidation.…”

mentioning

confidence: 99%

Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation

Ma¹,

Xiang²,

Zhou³

et al. 2019

ECS J. Solid State Sci. Technol.

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The influence of the ozone oxidation conditions on the interfacial and electrical properties of high-k/SiGe gate stacks was investigated by using a step-by-step fabrication procedure. The relationship between the electrical characteristics and the corresponding interfacial chemical structures revealed that a long oxidation time was necessary to obtain a high-quality interlayer (IL), whereas adverse in terms of interface state density (D it ) and equivalent oxide thickness (EOT) scaling. This conclusion suggested us to employ a posthigh-k-deposition oxidation (post-O) method to fabricate high-k/IL/SiGe gate stacks, in which the ozone oxidation was carried out after the deposition of the high-k layer. Compared with the step-by-step method, the post-O method could realize an ultrathin IL over a long oxidation time, owing to the reduced oxidation rate. Consequently, a well-balanced high-k/IL/SiGe gate stack with an ultrathin Ge-free IL of 0.26 nm, low gate leakage at V FB -1 of 6 × 10 −4 A/cm 2 , and D it as low as 2.2 × 10 12 eV −1 cm −2 was obtained.

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Comprehensive study of low temperature (< 1000 °C) oxidation process in SiGe/SOI structures

Cited by 6 publications

References 13 publications

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces

Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation

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Comprehensive study of low temperature (< 1000 °C) oxidation process in SiGe/SOI structures

Cited by 6 publications

References 13 publications

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO2/Al2O3 dielectric for a SiGe channel FinFET transistor

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO2/Al2O3 dielectric for a SiGe channel FinFET transistor

Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces

Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation

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Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor