Understanding the mechanisms impacting the interface states of ozone-treated high-<i>k</i>/SiGe interfaces

Ma, Xueli; Xiang, Jinjuan; Zhou, Lixing; Xu, Hao; Wang, Xiaolei; Yang, Hong; Li, Yongliang; Yin, Huaxiang; Wang, Wenwu

doi:10.1088/1361-6641/ab78f6

Cited by 3 publications

(4 citation statements)

References 27 publications

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“…could achieve a thin pure SiO x IL with a high ratio of Si 4+ components between the high-k dielectric and Si 0.7 Ge 0.3 . 19 Thus, the undesired GeO x in the IL with Ge dangling bonds was suppressed at the interface, and D it was reduced. Therefore, in situ O 3 passivation combined with an Al 2 O 3 /HfO 2 bi-layer gate dielectric was developed to improve its electrical performance, such as SS and leakage.…”

Section: Resultsmentioning

confidence: 99%

Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Cheng

Zhao

et al. 2021

ECS J. Solid State Sci. Technol.

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The fabrication process and electrical performance optimization of a high-mobility Si 0.7 Ge 0.3 channel FinFET device were systematically explored. A high-quality of Si 0.7 Ge 0.3 fin formation on Si substrates with shallow trench isolation-last (STI-last) scheme was first realized by a direct fin patterning and low-temperature STI annealing just after a blanket Si 0.7 Ge 0.3 film growth on Si substrate. To solve the process compatibility issue of the Si 0.7 Ge 0.3 fin, a new spacer etching process with CH 3 F/CF 4 -based plasma was developed because the existing spacer etching process is only appropriate for the Si fin and causes serious loss of the Si 0.7 Ge 0.3 fin due to its low selectivity. Moreover, rapid thermal annealing at 850 °C for 30 s was chosen as the optimal source/ drain (dopant activation process to maintain the thermal stability of the Si 0.7 Ge 0.3 fin. In-situ O 3 passivation, Al 2 O 3 /HfO 2 bi-layer gate dielectric, and an extra ground-plane doping implantation were identified as key factors for improving the electrical performance of the Si 0.7 Ge 0.3 channel FinFET device. Finally, a Si 0.7 Ge 0.3 channel FinFET device with a subthrehold swing of 87 mV dec −1 and an I on /I off ratio of 4e 5 was fabricated successfully using the proposed processes.

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Section: Resultsmentioning

confidence: 99%

Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Cheng

Zhao

et al. 2021

ECS J. Solid State Sci. Technol.

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“…Temperature and ozone oxidation time are two key parameters for the realization of a high-quality IL for Si 0.7 Ge 0.3 materials [23,24]. Also, Al 2 O 3 was selected as a high-k dielectric due to its good thermodynamic stability and high band gap [25,26].…”

Section: Ozone Oxidation For Si 07 Ge 03 Interface Qualitymentioning

confidence: 99%

“…In other words, under insufficient oxidation time conditions, Ge atoms trapped in the IL could not be fully oxidized and resulted in a poor interface [5,31]. Moreover, increasing the ozone oxidation time can contribute to an increase in the ratio of Si 4+ to Si 3+ between the high-k dielectric and the Si 0.7 Ge 0.3 layer, which helps to suppress the formation of GeO X in the IL and improves the D it [24]. Therefore, the low-temperature ozone oxidation at 300 • C for 30 min was chosen as optimal conditions for Si 0.7 Ge 0.3 interface passivation.…”

Section: Ozone Oxidation For Si 07 Ge 03 Interface Qualitymentioning

confidence: 99%

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Chen¹,

Li²,

Yao³

et al. 2022

Semicond. Sci. Technol.

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In this paper, the optimization of SiGe interface property for SiGe channel FinFET transistor is explored in detail. First, an optimal low-temperature ozone oxidation at 300 ℃ for 30 min was confirmed based on the Al2O3/Si0.7Ge0.3 MOS capacitors. This is because that a higher oxidation temperature and a longer oxidation time could suppress the formation of GeOX in the interface layer (IL), and significantly improve interface state density (Dit). Moreover, compared with Al2O3 sample, HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface property because the GeOX in the IL is more likely to diffuse into HfO2 layer. To further optimize the Dit and CET of Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersions characteristics and Dit have been improved significantly since the thin Al2O3 layer prevents the diffusion of GeOX to HfO2 layer and controls the growth of GeOX. Therefore, a high quality Si0.7Ge0.3 interface property optimization technology is realized by development of a low-temperature ozone oxidation (300 ℃, 30 min) combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 is obtained. The above result proves that these newly developed interface property optimization scheme is a practical technology for high mobility SiGe FinFET.

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“…To control the interface quality, many methods have been extensively explored, such as plasma (N 2 or NH 3 ) nitridation passivation [ 4 , 5 ], sulfur passivation [ 6 ], thermal oxidation [ 7 , 8 ], low-temperature ozone passivation [ 9 , 10 , 11 , 12 ] and Si-cap passivation [ 13 ]. Among them, low-temperature ozone passivation with low thermal budge and Si-cap passivation with excellent properties of interface are considered the most promising passivation methods.…”

Section: Introductionmentioning

confidence: 99%

Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

Yao

Wang

et al. 2021

Nanomaterials

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The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate.

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Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces

Cited by 3 publications

References 27 publications

Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

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Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces

Cited by 3 publications

References 27 publications

Fabrication of High-Mobility Si0.7Ge0.3 Channel FinFET for Optimization of Device Electrical Performance

Fabrication of High-Mobility Si0.7Ge0.3 Channel FinFET for Optimization of Device Electrical Performance

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO2/Al2O3 dielectric for a SiGe channel FinFET transistor

Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

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Product

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Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor