Test Cost Reduction Methodology for In-FO Wafer-Level Chip-Scale Package

Abstract

The Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies to achieve small chip form factor with low manufacturing cost. In InFO WLCSP, copper (Cu) pillars are used as contact interfaces without solder caps, which can be probed directly. The Cu pillars exposed in the air, however, will be oxidized gradually, which increases the resistance of contact interfaces, and leads to test quality loss. Increasing the number of touchdowns (NTD), i.e., probing more times, can help penetrate the oxide layers. However, it dirties the probe tips, and increases the contact resistance again. Probe tips can be cleaned by polishing, but increasing the polish count (NP) shortens the remaining lifetime of the probes, and increases the test time as well. To reduce the test time, the number of sites (dies) concurrently tested by a probe card, denoted as NS, can be increased, but it also increases the probe card cost. It therefore is clear that an optimization methodology should be developed, based on these competing parameters, in order to reduce the probing cost. In this work, we propose a cost model for analyzing the cost with respect to NTD, NP, and NS. With the proposed cost model, cost-effective probing configurations and procedures can be found effectively. Experimental results from an industrial case show that as much as 40.63% of the cost can be saved with NS=5, NTD=2, and the probe tips are polished after every 3 dies are probed. Index Terms-3D IC, cost model, InFO WLCSP, test cost analysis, wafer test, wafer probe I. INTRODUCTIONTo improve the power efficiency of a system and obtain both high data bandwidth and high system performance in a small form factor, TSV-based 3D integration technology is considered a promising approach [1]. However, TSV-based 3D IC is still expensive due to, e.g., expensive process of growing the redistribution layers [2] and forming the TSVs [3], so the TSVbased 3D integration is only suitable for high-end products [4]. To reduce the manufacturing cost of heterogeneous 3D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies [4], especially for mobile applications [4].In InFO WLCSP, copper (Cu) pillars are used as contact interfaces for direct probing without solder caps. Adopting Cu pillars has several benefits, e.g., small pitch size, thin thickness, and low power consumption. Cu pillars that are exposed in the air, however, will be oxidized gradually [4], which increases the contact resistance, resulting in test quality loss. The test quality of the DUTs is composed of two factors, i.e., test-escape rate (percentage of bad dies that passed the test) and over-kill

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