Test-data compression with low number of channels and short test time

Novák, Ondřej; Jenicek, Jiri; Rozkovec, Martin

doi:10.1109/ddecs.2014.6868772

Cited by 3 publications

(6 citation statements)

References 20 publications

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“…It was shown in [16] that it is possible to use an LFSR with state skipping [8], [20] instead of adding a phase shifter on the LFSR outputs. The state skipping LFSR performs successive jumps of constant length in its state sequence, since it omits a predetermined number of states by calculating directly the state after them.…”

Section: Decompression Hardwarementioning

confidence: 99%

“…This solution can be used if a characteristic LFSR polynomial guaranteeing periodic LFSR behavior with the period greater or equal to m*scan_chain_length is applied. This solution was applied in [16] with the characteristic LFSR polynomial of the form x m +x m-1 +1 as it is advantageous because of low hardware overhead. If the LFSR skips over m states the total number of XORs in the feedback is equal to m which is substantially lower than the number of XORs used in the phase shifter.…”

Section: Decompression Hardwarementioning

confidence: 99%

“…The maximum number of clock cycles gated before obtaining an m-bit fully controlled LFSR output is equal to m-1. The decoder efficiency depends on the average number of gated clk cycles [16].…”

Section: Decompression Hardwarementioning

confidence: 99%

“…In Fig. 4 we have plotted test lengths obtained by the simulation of test set compression according the algorithm from [16] for different branching the input signal to decompressor against the estimation of controllability according the measure 3. In order to fit the controllability values with the simulated test lengths we multiplied the controllability by a constant balancing the magnitudes with the test lengths.…”

Section: Decompression Hardwarementioning

confidence: 99%

“…This requirement can be considered a disadvantage of the method as other methods that do not guarantee full encode-ability of patterns can use shorter LFSRs [17]. Information about hardware overhead test coverage and test length of Smart BIST can be found in [16]. Still, it is not verified, which parameters of the decompressor are influencing the effectiveness of the decompression and how to establish sufficiently good tradeoff between hardware overhead and the test length.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

Novák

Jenicek

Rozkovec

2015

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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The paper discusses possibilities of rearranging test decompressor internal structure and linking its outputs with the parallel scan chain inputs in order to obtain better compression efficiency while the hardware overhead is not increased. We have experimentally verified that the controllability of decompressor outputs can be used as a simple and easily computable measure of the decompressor efficiency. Based on this observation we have developed a procedure that chooses a suboptimal LFSR outputs and parallel scan chain inputs interconnection. The procedure proposes a permutation of the scan chain inputs so that the scan chains that are fed with patterns with higher number of care bits are linked with the highly controllable decompressor outputs. We have experimentally verified on the benchmark circuits that adopting the proposed strategy improves the compression efficiency. Keywords-Design for testability (DFT), scan-based test, linear finite state machines, manufacturing test, test application time reduction, test data volume compression.

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Section: Decompression Hardwarementioning

confidence: 99%

Section: Decompression Hardwarementioning

confidence: 99%

Section: Decompression Hardwarementioning

confidence: 99%

Section: Decompression Hardwarementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

Novák

Jenicek

Rozkovec

2015

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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New scan compression approach to reduce the test data volume

Shantagiri

Kapur

Shastry

2021

IET Computers & Digital Tech

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The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic‐0 and logic‐1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

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Sequential test decompressors with fast variable wide spreading

Novák

Jenicek

Rozkovec

2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test patwith test vectors that have lower decodability as the number of free variables is limited by the test access mechanism bandwidth. We have found that it is possible to increase the number of free variables in the equations describing the care bits encoding by fast creating and wide spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We propose a decompressor combining a combinational linear decompressor and an LFSR like automaton that effectively distributes the free variables within the test pattern. The proposed test pattern decompressor outperforms the decodability of other decompressors with similar hardware overhead and it reduces the test time due to a possible reduction of the decompressor preloading.

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Test-data compression with low number of channels and short test time

Cited by 3 publications

References 20 publications

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

New scan compression approach to reduce the test data volume

Sequential test decompressors with fast variable wide spreading

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