Test data decompression for multiple scan designs with boundary scan

Rajski, J.; Tyszer, Jerzy; Zacharia, N.

doi:10.1109/12.736428

Cited by 82 publications

(45 citation statements)

References 15 publications

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“…This development is caused by an increasing complexity of the applied faults models as well as a growing demand for higher test quality. Despite significant advances of test compression approaches [2], it is highly important to improve the compaction of traditional scan patterns.…”

Section: Introductionmentioning

confidence: 99%

A new SAT-based ATPG for generating highly compacted test sets

Eggersglu

Krenz-Baath

Glowatz³

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In contrast to previous SAT-based ATPG techniques which were focused on dealing with hard single faults, the proposed approach employs the robustness of SAT-solvers to primarily push test compaction. Furthermore, a concept is introduced how the novel technique can be flexibly integrated into an existing industrial flow to reduce the pattern count. Experimental results on large industrial circuits show that the approach is able to reduce the pattern count of up to 63% compared to state-of-the-art dynamic compaction techniques.

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Section: Introductionmentioning

confidence: 99%

A new SAT-based ATPG for generating highly compacted test sets

Eggersglu

Krenz-Baath

Glowatz³

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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“…In BIST solutions, test patterns are generated by an on-chip pseudorandom pattern generator, usually a linearfeedback shift-register (LFSR). A number of BIST techniques based on test point insertion [Schotten and Meyr 1995], reseeding [Hellebrand et al 2000;Liang et al 2001;Rajski et al 1998], bit-flipping [Wunderlich and Kiefer 1996], bit-fixing [Touba and McCluskey 1996], and weighted random pattern testing [Wang 2001] have been proposed. Deterministic test patterns are applied in BIST by either controlling the state of the pattern generator [Hellebrand et al 2000;Krishna et al 2001;Liang et al 2001;Rajski et al 1998] or by altering the output of the pattern generator [Touba and McCluskey 1996;Wang 2001;Wunderlich and Kiefer 1996].…”

Section: Introductionmentioning

confidence: 99%

Scan-BIST based on cluster analysis and the encoding of repeating sequences

Wang

Chakrabarty

2007

ACM Trans. Des. Autom. Electron. Syst.

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We present a built-in self-test (BIST) approach for full-scan designs that extracts the most frequently occurring sequences from deterministic test patterns. The extracted sequences are stored on-chip, and are used during test application. Three sets of test patterns are applied to the circuit under test during a BIST test session; these include pseudorandom patterns, semirandom patterns, and deterministic patterns. The semirandom patterns are generated based on the stored sequences and they are more likely to detect hard-to-detect faults than pseudorandom patterns. The deterministic patterns are encoded using either the stored sequences or the LFSR reseeding technique to reduce test data volume. We use the cluster analysis technique for sequence extraction to reduce the amount of data to be stored. Experimental results for the ISCAS-89 benchmark circuits show that the proposed approach often requires less on-chip storage and test data volume than other recent BIST methods.

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“…One attractive approach for test data compression is to use Linear Feedback Shift Register (LFSR) reseeding [11]. Several methods based on LFSR reseeding have been proposed [6] [12] [13] [18] [20] [26]. Commercial tools based on LFSR reseeding have also been developed recently which include Mentor Graphics' TestKompress [21] and Synopsys' DBIST [24].…”

Section: Introductionmentioning

confidence: 99%

Combining dictionary coding and LFSR reseeding for test data compression

Sun

Kinney

Vinnakota

2004

Proceedings of the 41st Annual Design Automation Conference

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In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the compression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.

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Test data decompression for multiple scan designs with boundary scan

Cited by 82 publications

References 15 publications

A new SAT-based ATPG for generating highly compacted test sets

A new SAT-based ATPG for generating highly compacted test sets

Scan-BIST based on cluster analysis and the encoding of repeating sequences

Combining dictionary coding and LFSR reseeding for test data compression

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