Test generation for sequential circuits using individual initial value propagation

Ogihara, Takuji; Saruyama, Shuichi; Murai, Shinichi

doi:10.1109/iccad.1988.122573

Cited by 16 publications

(3 citation statements)

References 9 publications

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“…bios), transistors (no. We assumed that faults in the clock control logic could be detected using the individual initial value propagation method [20], and these faults were not considered. latches) are listed.…”

Section: Resultsmentioning

confidence: 99%

Generation and evaluation of current and logic tests for switch-level sequential circuits

Chen

Abraham

1992

J Electron Test

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This article presents an approach to developing high quality tests for switch-level circuits using both current and logic test generation algorithms. Faults that are aborted or undetectable by logic tests may be detected by current tests, or vice versa. An efficient switch level test generation algorithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.

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Section: Resultsmentioning

confidence: 99%

Generation and evaluation of current and logic tests for switch-level sequential circuits

Chen

Abraham

1992

J Electron Test

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“…In [7], the idea of using multiple X-symbols is discussed for the first time. The use of RSL during the forward implication step in topological test pattern generation is proposed in [8,9]. Yet, there has been no complete ATPG algorithm that also uses RSL during the backward implication step.…”

Section: Introductionmentioning

confidence: 99%

Test pattern generation in presence of unknown values based on restricted symbolic logic

Erb

Scheibler

Kochte

et al. 2014

2014 International Test Conference

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Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618x faster than the QBF-based solution, more scalable and more robust.

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“…The CPU time liniit in all cases was 20 seconds. We assumed that faults in the clock control logic could be detected using the individual initial value propagation method [17], and these faults were not considered. All the test generation result,s are from a SUN 4/280.…”

Section: Resultsmentioning

confidence: 99%

High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms

Chen¹,

Abraham²

1991, Proceedings. International Test Conference

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This paper presents an approach to developing high quality tests for switch-level circuits using both current. and logic test generation algorithms. Clear definitions for analyzing the effectiveness of the joint !,est generation approach are derived. Results on a set of switch-level circuits show very high coverage of stuickat, st,uck-on, and stuck-open faults when both current and logic tests are used.

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Test generation for sequential circuits using individual initial value propagation

Cited by 16 publications

References 9 publications

Generation and evaluation of current and logic tests for switch-level sequential circuits

Generation and evaluation of current and logic tests for switch-level sequential circuits

Test pattern generation in presence of unknown values based on restricted symbolic logic

High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms

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