Test Pattern Modification for Average IR-Drop Reduction

Ding, Weisheng; Hsieh, Hung-Yi; Han, Chong; Li, James Chien-Mo; Wen, Xiaoqing

doi:10.1109/tvlsi.2015.2391291

Cited by 8 publications

(4 citation statements)

References 34 publications

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“…Techniques using layout information † [12], [19], [20], [22], [25], [29], [38] † -Sections 4 and 5 do not have separate sub-sections for these techniques. They are covered as part of other sub-sections.…”

Section: Classificationmentioning

confidence: 99%

“…Assigning multiple bits at a time significantly reduces the CPU time and produces better IR-drop cost reduction compared to [23]. Ding et al [25] presented a test pattern modification method to reduce capture cycle-induced IR-drop in hotspots. It calculates IR-drop contributions by every node to the nodes in the hotspot region and modifies only a few don't care bits rather than modifying all don't care bits.…”

Section: Pattern Optimization Techniques 51 X-fillingmentioning

confidence: 99%

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A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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Section: Classificationmentioning

confidence: 99%

Section: Pattern Optimization Techniques 51 X-fillingmentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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“…The power consumption of these digital ICs during test has also grown dramatically, which is significantly higher than the power consumed during the functional mode due to the high switching activity of combinational circuits during test vector shifting [1]. High scan shifting power leads to excessive heat dissipation and IR drop as well as unrealistic timing failures [2], leading to lower circuit reliability and reduced manufacturing yield. Therefore, low-power test techniques are highly demanded.…”

Section: Introductionmentioning

confidence: 99%

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

Cao

Jiao

Marinissen

2022

IEEE Trans. Circuits Syst. II

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published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal.If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User

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“…Other types of tests that attempt to achieve close-to-functional operation conditions are described in [10][11][12][13]. In addition, low-power test generation procedures that attempt to maintain a functional level of power dissipation are described in [14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

On‐chip generation of primary input sequences for multicycle functional broadside tests

Pomeranz

2018

IET Computers & Digital Techniques

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Functional broadside tests are important for avoiding overtesting of delay faults during the application of scan-based tests. Multicycle tests have advantages in defect detection and test compaction. This study addresses the on-chip generation of primary input sequences for the application of multicycle functional broadside tests to a circuit that is embedded in a larger design. In this study, multicycle functional broadside tests are considered under two types of constraints: (i) functional constraints that the design imposes on the primary input patterns of the circuit, and (ii) test application constraints when direct access to the primary inputs of the circuit is not available, and the application of two or more consecutive primary input patterns requires hardware support. The use of multicycle functional broadside tests also results in an increased fault coverage.

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Test Pattern Modification for Average IR-Drop Reduction

Cited by 8 publications

References 34 publications

A survey of scan-capture power reduction techniques

A survey of scan-capture power reduction techniques

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

On‐chip generation of primary input sequences for multicycle functional broadside tests

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