Test quality of asynchronous circuits: a defect-oriented evaluation

Roncken, Marly; Bruls, E.M.J.G.

doi:10.1109/test.1996.556963

Cited by 22 publications

(19 citation statements)

References 21 publications

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“…Every apriori step is one fewer heuristic rule in test pattern generation, and as such reduces the complexity of the algorithms. The same argument holds for the abovementioned related works reported in [11] [15], where handshake components are used as building blocks for designing asynchronous circuits [16]. In addition, our analysis identifies the transistor-level stuck-at faults that are not detectable by Boolean testing.…”

Section: Introductionsupporting

confidence: 62%

“…Some faults may only be detected by an Iddq test [14], some cause oscillation which may or may not be detectable, and some can make the circuit speed-dependent. · [15] presents fault analysis results for handshake control components, injecting all (gate-level) stuck-at faults and all (transistor as well as gate-level) bridging faults. As test detection strategies, the authors use logic voltage (Boolean) testing and IDDQ.…”

Section: Introductionmentioning

confidence: 99%

“…The main contributions of this paper are: · We go beyond the C-element and analyze various implementations of basic elements used in delayinsensitive asynchronous designs. These elements are different from those analyzed in [11] [15]. · We introduce a set of faults, namely down-enabled, upenabled, down-disabled and up-disabled faults that together with the stuck-at fault model can capture most of the faulty behaviors of these basic elements, independent of their internal implementation.…”

Section: Introductionmentioning

confidence: 99%

“…The corresponding abstraction can be used in test pattern generation. · Using DUDES, we set the basis for a formal framework for fault collapsing, which we think can be used as a theoretical foundation for explaining the experimental analysis results in [15]. The main purpose of the DUDES fault model is to significantly reduce the complexity of fault simulation, fault grading and test pattern generation in four ways: · DUDES faults enable fault simulation at the logic level (network of basic elements) instead of at the transistor level, without jeopardizing the test quality.…”

Section: Introductionmentioning

confidence: 99%

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DUDES: a fault abstraction and collapsing framework for asynchronous circuits

Shirvani

Mitra

Ebergen

et al.

Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00

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This paper addresses the problem of fault collapsing in asynchronous circuits. We investigate different transistor-level implementations of some basic elements that are used in delay-insensitive asynchronous circuit designs, and analyze them in the presence of single stuckat faults. From this analysis, we conclude that all internal stuck-at faults which are detectable by Boolean testing, can be represented as pin-faults. This abstraction makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time. We show how this fault model, called DUDES, can be used for fault collapsing to reduce the size of fault lists at the logic level, thereby reducing the simulation time even further. We set the basis for a formal technique for deriving equivalence relationships among the faults under consideration, using trace expressions, and illustrate that this formal technique also supports fault collapsing at the system level. This framework can be expanded to a theory of fault abstraction and collapsing for asynchronous circuits that can reduce the complexity of test pattern generation and fault simulation.

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Section: Introductionsupporting

confidence: 62%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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DUDES: a fault abstraction and collapsing framework for asynchronous circuits

Shirvani

Mitra

Ebergen

et al.

Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00

Self Cite

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“…Despite the growing number of recent efforts in the specification and design of asynchronous circuits, testing of these circuits has not been explored to any great degree. Very few efforts have been made in this area compared to efforts in synchronoustesting [11,13,14,18,19,20,21,22,23,27].…”

Section: Introductionmentioning

confidence: 99%

ACT: a DFT tool for self-timed circuits

Khoche

Brunvand

Proceedings International Test Conference 1997

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This paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based selftimed circuits testable. The ACT tool is the first oFits kind for testing macro-module based self-timed circuits. ACT modifies designs automatically to incorporate partial scan and provides a complete path from schematic capturie to physical layout. It also has a test generation system to generate vectors for the testable design and to compute fault coverage of the generated tests. The test generatioin system includes a module for doing critical hazard free (.est generation using a new 6-valued algebra. ACT has been h i l t around commercial tools from Viewlogic and Cascade. A Viewlogic schematic is used as the design entry point and Cascade tools are used for technology mapping.

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