Test Structure Design, Extraction, and Impact Study of FEOL Capacitance Parameters in Advanced 45nm Technology

Abstract

In the advanced Low Power (LP) CMOS technology nodes gateto-source/drain overlap capacitance (Cov), gate-to-contact capacitance (CcO) and gate sidewall fringe capacitance (Cf) have become increasingly important component(s) of transistor parasitic. Accurate extraction and modeling of these parasitic are essential in accurate estimation of circuit performance. In this paper we describe test structure design and extraction of these parasitic components from silicon, which we later correlate to circuit performance. SPICE simulations were performed to substantiate the measurements as needed.

Power estimation technique for deep submicrometer conventional MOS transistors

“…Various power estimation techniques [1], [2], [3], [4] for MOS transistors using load capacitances have been introduced previously. The load capacitance in "(9)" consists of parasitic, gate and wire capacitances.…”

“…Several models for parasitic capacitances have been proposed in [1], [2], [3], [4]. These models are efficient, but they cannot estimate accurately.…”

Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40nm technology

“…Meanwhile, with layout-dependent coefficients such as gate to contact space (CPS) and contact to contact space (CCS) decreasing, gate-to-source/drain fringing capacitance (C f ) and gate to contact capacitance (C co ) should not be neglected any more in total MOSFET parasitic capacitance [3]. It is necessary to extract C f and C co accurately in both digital and RF circuit simulation because C f and C co occupy more and more significant position [4,5].…”

Efficient power macromodeling technique for conventional MOS transistors

“…In response to second objective, the parasitic capacitances are becoming an important issue for designing the logic circuits with aggressive reduction of MOS transistor dimensions into the deep sub micrometer regime [1], [2], [3], [4]. In digital applications, these parasitic capacitances have strong impact on propagation delay and overall power dissipation of the circuit.…”