Test Structure Design for Precise Understanding of Cu/Low-k Dielectric Reliability

Abstract

Single line test structures are suggested for failure analysis and reliability improvement development, apart from using the conventional comb test structures. This is due to the challenges in controlling the damage after electrical tests as well as in pin-pointing sub-surface failures with present techniques. Three failure modes were observed in the new test structure, which can be identified by its I-V leakage characteristics. These also demonstrate the importance of including different geometrical layouts for backend reliability characterization. [Keywords: carbon-doped low-k dielectric, delamination, Ta ion diffusion, single line test structure]

Electrical Breakdown in Advanced Interconnect Dielectrics

“…The damage zone under TDDB stress is usually smaller than that found by RVDB because the dissipated charge during breakdown is somewhat smaller. Interestingly, unpublished work has shown that, even in the tiniest of IMD capacitors ('end-to-end' pointed finger capacitors for a 65 nm node interconnect [252] using an LK dielectric, which is somewhat similar to that shown by Tan et al [253]) undergoing IMD-TDDB stress, obvious physical damage to the dielectric will only be evident after an actual HB event occurs but not prior to that, even during the latter stages of the defect-generation period [303]. In that case, shorting damage will be evident where the barrier has failed [300], although, again, unambiguously identifying that site as the trigger site is difficult at best.…”

“…The types of test structure used to assess LK/ULK IMD reliability and process quality [247,248] are either comb-comb (CC, or fork-fork, FF) or comb-serpent (CS, or meanderfork, MF) structures (see Figures 11.4 (a) and (b)). Specialized structures that can test nanoscale ('end-to-end' or 'tip-to-tip') dielectric breakdown [252][253][254] or consist entirely of line terminations or meanders (see Figure 11.4 (c) ) can be constructed as well [239,255]. Also, the number of repeats of these paired lines can be varied, and the main limitation to these structures may be the permissible test structure size on a given test chip.…”

Degradation in TDDB of Cu/low-k test structures due to field interaction between adjacent metal lines

“…Hence there is a need to study the reliability of this system. Small area test structures were originally designed by Tan et al for the purpose of studying failure analysis of low-k dielectric [1]. This structure also mimics some shape and area that may be found in the real test structures, but are not represented by the conventional comb structures often used for reliability studies of dielectric breakdowns [2].…”

Investigation of interconnect layout on CU/Low-K TDDB reliability

“…image of Metal 1 circuit layout is shown in Fig. 1 [85], which is one of the common geometry seen in the actual layout design. Due to the difference in geometry and area between the small area and conventional test structures, more study should be done to understand how the data gathered from the small area test structures relate to the conventional structure.…”