Testability features of the 68040

Abstract

This paper describes the design and implementation of onchip test functions on the 68040 microprocessor. The discussion includes an introduction to the 68040 along with the testability goals and objectives that were set in the beginning of the design. Further discussions detail the different design for testability (DFT) techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the intemal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.

On the yield of VLSI processors with on-chip CPU cache

“…For estimating the area that the on-chip cache occupies, we used the area model presented in [16]. The choice h k h tg h dt is based on the fact that cache arrays are fabricated with the tightest feature and scaling rules available in a given technology which means that caches are more susceptible to faults [17], [18]. Only experimental data obtained by monitoring wafers can show which values of h k , h tg , and h dt must be used in the yield expression.…”

A cache-defect-aware code placement algorithm for improving the performance of processors

“…For example in StrongARM SA-110 processor, one half of the total chip area is devoted to the two 16KB caches [6]. Since cache arrays are designed with the tightest feature and scaling rules available in a given technology, they are more susceptible to faults compared to logic blocks [7] [8]. Thus, the yield of microprocessors with on-chip caches can be enhanced considerably if cache defects are tolerated without noticeable performance degradation.…”