Testing gigabit multilane SerDes interfaces with passive jitter injection filters

Laquai, B.; Cai, Yi

doi:10.1109/test.2001.966645

Cited by 18 publications

(2 citation statements)

References 2 publications

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“…There are no many choices right now that can do multigigabit devices jitter compliance testing in production. Most jitter test solutions are based on lab instruments, extra on-chip circuitry, or DUT board add-on modules [13][14][15][16]. These solutions are limited either by its low throughput, low accuracy and repeatability, or by the high design complexity of the device or the loadboard.…”

Section: Introductionmentioning

confidence: 99%

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata

Fan¹,

Cai²,

Žilić³

2007

2007 IEEE International Test Conference

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Jitter test in production is notorious for its long test time and the challenge of accuracy verification. Among various types of jitter, Random Jitter (RJ) is most challenging to test on Automatic Test Equipment (ATE) because of its randomness. To be considered as a favorable jitter test in production for multi-gigabit devices, the RJ needs to be measured with sub-picosecond accuracy and the whole test time is expected to be in a few tens of milliseconds. However, no known solutions meet these criteria to our best knowledge. In this paper, we present a systematic solution for multiple Giga-bit-per-second (Gbps) Transmitter (TX) jitter testing on ATE. Our undersampling-based solution extracts jitter either from edge histograms in time domain or from the jitter spectrum in frequency domain. Both approaches provide a RJ precision better than ±0.5ps and are capable of finishing the whole TX test within 100ms. We have verified the solution with data rates up to 6Gbps and applied it in mass production.

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Section: Introductionmentioning

confidence: 99%

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata

Fan¹,

Cai²,

Žilić³

2007

2007 IEEE International Test Conference

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show abstract

“…Production testing can utilize lower cost approaches that maintain good parametric fault coverage (e.g. parametric loopback [1,2]) to screen devices. However, to properly enable this lower cost production test method it is important in the characterization and design validation phases to use at-speed testing with high quality measurement accuracy.…”

Section: Introductionmentioning

confidence: 99%

Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications

Moreira¹,

Barnes²,

Hoersch³

2007

2007 IEEE International Test Conference

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Relays are some of the most frequently used components on test fixtures for automated test applications. With datarates of current I/O interfaces already reaching 5Gbps and beyond in desktop applications and expected to continue to increase, test engineers must make the decision to continue using relays on the high-speed signal lines, or remove the relays from the test fixture signal paths and sacrifice the flexibility they provide. This paper presents some results and guidelines on using relays in test fixtures for 10Gbps applications. A commercially available relay was selected and integrated into a typical ATE test fixture design. Special consideration was given to the footprint optimization through 3D-EM simulation and the use of passive equalization to compensate for some of the relay losses. The paper concludes with measurements of an experimental test fixture using an ATE system running 10Gbps.

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Design for Test and Testability

Meixner¹,

Gullo²

2021

Design for Maintainability

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Testing gigabit multilane SerDes interfaces with passive jitter injection filters

Cited by 18 publications

References 2 publications

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata

Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications

Design for Test and Testability

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