Testing high-speed IO links using on-die circuitry

Iyer, Prakash; Jain, Sakshi; Casper, Bryan; Howard, Jason D.

doi:10.1109/vlsid.2006.159

Cited by 9 publications

(4 citation statements)

References 5 publications

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“…3, to avoid selecting a combination of too-high sensitivity. Due to the large number of EQ maps, finding the optimal subset of coefficients is usually a very challenging task, considering the large number electrical parameters, and the multiplicity of signal eyes that are produced by on-die probes [15] for observation. Fig.…”

Section: Transmitter Equalization Coefficient Matrixmentioning

confidence: 99%

Direct optimization of a PCI express link equalization in industrial post-silicon validation

Rangel-Patiño

Rayas‐Sánchez

Vega-Ochoa

et al. 2018

2018 IEEE 19th Latin-American Test Symposium (LATS)

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Post-silicon validation is a crucial industrial testing process in modern computer platforms. Post-silicon validation of high-speed input/output (HSIO) links can be critical for making a product release qualification. Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry, and one of the most complex HSIO interfaces. PCIe data rates increase on every new generation. To mitigate channel effects due to the increase in transmission speeds, the PCIe specification defines requirements to perform equalization (EQ) at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients, which are obtained by measuring the eye height, eye width, and the eye asymmetries of the received signal. Given the large number of electrical parameters and the multiplicity of signal eyes that are produced by on-die probes for observation, finding this subset of coefficients is often a challenge. In order to overcome this problem, a direct optimization method based on a suitable objective function formulation to efficiently tune the Tx and Rx EQ coefficients to successfully comply with the PCIe specification is presented in this report. The proposed optimization approach is based on a low-cost computational procedure combining pattern search and Nelder-Mead methods to efficiently solve an objective function with many local minima, and evaluated by lab measurements on a realistic industrial postsilicon validation platform.

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Section: Transmitter Equalization Coefficient Matrixmentioning

confidence: 99%

Direct optimization of a PCI express link equalization in industrial post-silicon validation

Rangel-Patiño

Rayas‐Sánchez

Vega-Ochoa

et al. 2018

2018 IEEE 19th Latin-American Test Symposium (LATS)

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“…For I/O links, we have simulation data (SPICE-level for individual modules, and behavioral simulation for statistical eye analysis [7]), on-die test structures that monitor process variations [8], tester data [9], [10], and so on. During validation, we may also read out a few key run-time parameters such as equalization coefficients.…”

Section: B Integrating Multiple Sources Of Datamentioning

confidence: 99%

Challenges in post-silicon validation of high-speed I/O links

2012

Proceedings of the International Conference on Computer-Aided Design

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There are increasingly number of analog/mixedsignal circuits in microprocessors and SOCs. A significant portion of mixed-signal circuits are high-speed I/O links, including serial buses such as PCIE and parallel buses such as DDR. Post-silicon validation of I/O links is hard and time-consuming, and can be critical for making a product release qualification decision. In this paper, we try to summarize key challenges in post-silicon I/O validation. We discuss potential research directions and potential solutions to improve efficiency and quality of I/O validation.

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“…84) and its application to testing HSSL was reported in Ref. 85). The waveform capture circuit, functioning like an on-chip oscilloscope, is made possible by sweeping a set of timing phases and voltage levels and by checking the bit error rate with respect to each of these settings.…”

Section: Dft Techniques For Equalizers In Hsslmentioning

confidence: 99%

Recent Advances in Analog, Mixed-Signal, and RF Testing

Cheng

Chang

2010

IPSJ Transactions on System LSI Design Methodology

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Due to the lack of widely applicable fault models, testing for analog, mixedsignal (AMS), and radio frequency (RF) circuits has been, and will continue to be, primarily based on checking their conformance to the specifications. However, with the higher level of integration and increased diversity of specifications for measurement, specification-based testing is becoming increasingly difficult and costly. As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost. This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends. In addition, we introduce several low-cost testing paradigms including the loopback testing, alternate testing, and digitally-assisted testing that offer the promise of significant test cost reduction with little or even no compromise in test quality. Moving forward, in addition to screening the defective parts, testing will play an increasingly important role in supporting other post-silicon quality assurance functions such as post-silicon validation, tuning, and in-field reliability of system chips.

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Testing high-speed IO links using on-die circuitry

Cited by 9 publications

References 5 publications

Direct optimization of a PCI express link equalization in industrial post-silicon validation

Direct optimization of a PCI express link equalization in industrial post-silicon validation

Challenges in post-silicon validation of high-speed I/O links

Recent Advances in Analog, Mixed-Signal, and RF Testing

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