Testing Methodology of Embedded DRAMs

Abstract

The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

Conceptual Design of a Nano-Networking Device

“…The cell size reported for a 14 nm FinFET SRAM cell is 0.064 µm 2 [49], which involves a feature size of 327 F 2 . Nevertheless, this traditional conception is changing since new SRAM and DRAM architectures [50,51] integrate features of both RAM types. In [50], the authors designed a capacitor-less DRAM cell, called A-RAM.…”

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

“…During a refresh operation the contents of each memory word are read, refreshed through the Refreshment Register and written back. Due the limited external access, testing e-DRAMs is more challenging than testing monolithic DRAM chips [4]- [8]. On-line checking based on error detecting codes has been proposed to deal with soft errors occurring during system operation.…”

Contribution to the design of nanodevices and communication protocols for nanonetworks in the THz band

“…The cell size reported for a 14nm FinFET SRAM cell is 0.064 µm 2 [49], which involves a feature size of 327 F 2 . Nevertheless, this traditional conception is changing since new SRAM and DRAM architectures [50,51] integrate features of both RAM types. In [50], the authors designed a capacitor-less DRAM cell, called A-RAM.…”