TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature Variations

Abstract

With the continuous scaling of CMOS technology, microelectronic circuits are increasingly susceptible to microelectronic variations such as variations in operating conditions. Such variations can cause delay uncertainty in microelectronic circuits, leading to timing errors. Circuit designers typically combat these errors using conservative guardbands in the circuit and architectural design, which can, however, cause significant loss of operational efficiency. In this paper, we propose TEVoT, a supervised learning model that can predict the timing errors of functional units (FUs) under different operating conditions, clock speeds, and input workload. We perform dynamic timing analysis to characterize the delay variations of FUs under different conditions, based on which we collect training data. We then extract useful features from training data and apply supervised learning methods to establish TEVoT. Across 100 different operating conditions, 4 widely-used FUs, 3 clocking speeds, and 3 datasets, TEVoT achieves an average prediction accuracy at 98.25% and is 100X faster than gate-level simulation. We further use TEVoT to estimate application output quality under different operating conditions by exposing circuit-level timing errors to application level. TEVoT achieves an average estimation accuracy at 97% for two image processing applications across 100 operating conditions.

Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning

“…The considered execution history depends on the target design. In contrast to existing error prediction models, the developed microarchitecture-aware model is able to predict timing errors at bit-level across different types of instructions, removing the need for different models for each individual operation as needed by existing frameworks [5], [9].…”

“…TPR and TNR, provide a complementary view of the performance of our approach even under imbalance data as opposed to Acc [5]. Note that existing relevant studies have only considered Acc which may be ambiguous [5], [9].…”

“…We compare the output of our model to the golden output provided from DTA and state-of-the-art approach where d = 2 [5], [9]. Note that we compare our final model with our 64-bit model where d = 2, as state-of-the-art approaches [5], [9] have multiple models, targeting a single instruction type each time, while we combine multiple instruction types in a single model.…”

“…We incorporate, for the first time, more complex microarchitecture features during the execution of various instructions in a pipelined core, such as the instruction execution history (i.e., order and type of instructions within a pipeline at any instant) into timing error modelling. Our model jointly considers several instruction types, rather than separate models for each individual instruction [5], [9], to predict the exact error location accurately, allowing the interpretation of error significance. Our results verify that deeper execution history leads to up to 11% accuracy improvement when compared to existing works that considered only one previous instruction [5], [9].…”

“…Our model jointly considers several instruction types, rather than separate models for each individual instruction [5], [9], to predict the exact error location accurately, allowing the interpretation of error significance. Our results verify that deeper execution history leads to up to 11% accuracy improvement when compared to existing works that considered only one previous instruction [5], [9]. • We validate the efficacy of SCVF by comparing the error-induced quality loss obtained by the ML prediction model and the quality loss observed for the instruction sequences (ISQs) that we extract from a representative set of benchmarks.…”