The CDB/HCDB semiconductor wafer representation server

Walker, D.M.H.; Kellen, C.; Svoboda, David; Strojwas, Andrzej J.

doi:10.1109/43.205008

Cited by 23 publications

(4 citation statements)

References 20 publications

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“…The process simulator creates a 3-D representation of the resonator structure consisting of hierarchically connected layers of material known as the Chip Data Base (CDB) [39]. CDB is created from the MUMPS process flow and the CIF layout of the resonator.…”

Section: B Structure Extractionmentioning

confidence: 99%

CARAMEL: Contamination And Reliability Analysis of MicroElectromechanical Layout

Kolpekwar

Jiang²,

Blanton³

1999

J. Microelectromech. Syst.

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CARAMEL (Contamination And Reliability Analysis of MicroElectromechanical Layout) is a CAD tool for MEMS fault model generation. It is based on the integrated circuit contamination analysis tool CODEF [1] and is capable of analyzing the impact of contamination particles on the behavior of microelectromechanical systems. CARAMEL's simulation output indicates that a wide range of defective structures are possible due to the presence of particulate contaminations. Moreover, electromechanical simulations of CARAMEL's mesh representations of defective layout has revealed that a wide variety of misbehaviors are associated with these defects. Several thousand contamination simulations were performed using CARAMEL on the surface micromachined comb-drive resonator. The results generated by CARAMEL identifies the comb drive as the most defect prone region of the microresonator and the deposition of the first structural layer as the most vulnerable processing step.

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Section: B Structure Extractionmentioning

confidence: 99%

CARAMEL: Contamination And Reliability Analysis of MicroElectromechanical Layout

Kolpekwar

Jiang²,

Blanton³

1999

J. Microelectromech. Syst.

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“…The first one relies on local flattening of the design hierarchy [1], [2]. The second one applies decomposition of cells into parts based on interactions of their instances with the surrounding primitives and other instances which "cleans" the hierarchy at the expense of an increase in the number of cells [3], [4]. Third approach adds some complexity to hierarchy by applying the inverse layout trees [5].…”

Section: Introductionmentioning

confidence: 99%

A pattern matching algorithm for verification and analysis of very large IC layouts

Niewczas

Maly

Strojwas

1998

Proceedings of the 1998 International Symposium on Physical Design

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We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the information stored within the pattern and position of the pattern instance. We also show preliminary results of analysis of the state-of-the-art ICs which suggest that the diversity of patterns does not significantly increase with the increase of chip size.

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“…4 fabrication process in the PREDITOR format [17], [18], and (c) statistics of contamination parameters in each processing step of interest.…”

Section: Contamination-fault Mapper Codef [16]mentioning

confidence: 99%

Inductive contamination analysis (ICA) with SRAM application

Khare

Maly

Proceedings of 1995 IEEE International Test Conference (ITC)

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This paper proposes a new simulation-based fault modeling methodology. The methodology -an extension of Inductive Fault Analysis -uses the contamination-defectfault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions. The application of this methodology (called Inductive Contamination Analysis) is demonstrated by development of SRAM fault models.

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The CDB/HCDB semiconductor wafer representation server

Cited by 23 publications

References 20 publications

CARAMEL: Contamination And Reliability Analysis of MicroElectromechanical Layout

CARAMEL: Contamination And Reliability Analysis of MicroElectromechanical Layout

A pattern matching algorithm for verification and analysis of very large IC layouts

Inductive contamination analysis (ICA) with SRAM application

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