The challenge of ultra thin chip assembly

Feil, Michael; Adler, Charles L.; Hemmetzberger, Dieter; König, M.; Bock, Karlheinz

doi:10.1109/ectc.2004.1319312

Cited by 35 publications

(25 citation statements)

References 2 publications

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“…In the case of UTCs packaged or embedded in thin foils, 103 several other factors, including increased thickness and the bonding/embedding, influence the bendability as compared to the blank or stand-alone dies. The controlled bending of such chips during characterization is achieved by FIG.…”

Section: A Uniaxial Bending Of Utcsmentioning

confidence: 99%

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Heidari

Wacker

Dahiya

2017

Applied Physics Reviews

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Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

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Section: A Uniaxial Bending Of Utcsmentioning

confidence: 99%

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Heidari

Wacker

Dahiya

2017

Applied Physics Reviews

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“…Fine-pitch interconnection, also at a 20 µm pitch for silicon-on-silicon connections with TSVs, has also been reported by [25] and also variety of bonding and electrical interconnection approaches between silicon die in thinned silicon die, die stacks, or packages using silicon reported in [26,27]. In these interconnection examples, anisotropic conductive polymers were used to bond 25 µm thinned dies with 50 µm pitch AuSn bumps.…”

Section: Historical Evolution Of 3d System Integrationmentioning

confidence: 91%

“…In these interconnection examples, anisotropic conductive polymers were used to bond 25 µm thinned dies with 50 µm pitch AuSn bumps. Technical publications have also reported fine-pitch solder connections to copper as a means either to stack thinned silicon chips to other silicon dies or to join dies to silicon packages [25][26][27][28]. An application that leverages TSVs and fine-pitch interconnections with demonstration of functioning memory die stacks has also been presented [29].…”

Section: Historical Evolution Of 3d System Integrationmentioning

confidence: 99%

Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter. IntroductionThe ongoing demand for greater functionality resulting in multiple IC products, longer off-chip interconnects ravage the performance of microelectronic systems. The advent of System-on-Chip (SoC) in the mid 1990s primarily addressed the increasing delay of the off-chip interconnects. Integrating all of the components on a monolithic substrate enhances the overall speed of the system, while decreasing the power consumption. To assimilate disparate technologies, however several difficulties must be surmounted to achieve high yield for the entire system. Additional system requirements for the radio frequency (RF) circuitry, passive elements, and discrete components, such us decoupling capacitors, which are not easily integrated due to performance degradation or size limitations. While Moore's law [1] and the pursuit of ever increasing transistor counts is well known in IC design and manufacturing circles, what is seldom brought to light for others, are the escalating cost and technology challenges associated with this pursuit. Smaller transistors and larger dies have been reasonable answer to this quest in the past. Stacked dies using wire bond connections and flip-chips have even been employed to create system-in-package (SiP) solutions that meet the needs of some. Looking for alternative solutions for next generation designs, that meet the performance, integration, form-factor, manufacturability, and cost requirements, may have begun to look at going up rather than out. With this trend, the Three-dimensional (3D) integration using through-silicon via (TSV) technology has gained much attention. Once the domain of specialist applications, more mainstream users, such as memories, microprocessors ans specialized logic designs are now being considered as TSV candidates. The advantages of 3D-IC integration are better electrical performance, low power consumption, lower area and weight and high performance (Fig. 2.1). Opportunities for Three-Dimensional IntegrationPerformance requirements such as increased band...

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“…The pick-and-place equipment conventionally used for direct chip attachment cannot satisfactorily handle ultrathin and small dice [12,18]. One of the reasons is that these dice are very fragile and tend to be easily damaged.…”

Section: Contact Methods For Ultrathin Die Packagingmentioning

confidence: 99%

“…Only methods for ultrathin wafer processing that require limited transfers between the wafer carriers can provide reliable operations with high throughput at low production cost. Consequently, a process called ''Dicing-By-Thinning'' or ''Dicing-Before-Grinding'' was suggested [4,[16][17][18][19] in which halfcut dicing is carried out on the wafer's front side before thinning. After bonding to a handle wafer or backgrinding tape, the half-diced wafer is thinned by backgrinding until trenches are opened and dice separated.…”

Section: Wafer Dicingmentioning

confidence: 99%