High costs are a key challenge in “democratization” of organ-chip research. We present a low-resource barrier-on-chip based on tape, and use it to model small intestine and its response to chili peppers (capsaicinoids).

Because of their low height, the low assembly topography and their mechanical flexibility, ultra thin chips (about 20 µm) offer a wide field of possible applications. During the last years, we have successfully investigated in production, handling and assembly processes for such thin ICs. The chip handling and assembly processes had to be adapted to the very thin material, beginning with the development of special “Dicing by Thinning” process. A new pick and place process using thermal releasable tapes has been developed. For the chip assembly and contacting various methods depending on the application are available. The complete process chain from wafer processing up to the assembled ultra thin IC together with some application examples is discussed

Purpose - The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips. Design/methodology/approach - Methods to embed chips in flex include flip-chip assembly and subsequent lamination, or the construction of a separate ultra-thin chip package (UTCP) using spin-on polyimides and thin-film metallisation technology. Thinning and separation of the chips is done using a "dicing-by-thinning" method. Findings - The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 mu m package where also the 20 mu m thick chip is bendable. Research limitations/implications - Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demonstrators using the developed technologies. Originality/value - Thinning down silicon chips to thicknesses of 25 mu m and lower is an innovative technology, as well as assembly and embedding of these chips in flexible substrates

Cost effective and high quality processes are needed for further development of flexible electronic systems. Applications of these structures are e. g. in the field of high density interconnection foils or polymer electronics. In this paper a lithography process for patterning copper on flexible foils using reel-to-reel methods is presented. The process allows the fabrication of well defined copper structures with typical feature sizes from 15 to 40 µm using either etching or electro plating technology. Properties of the dry film photoresist used in the process as well as details of the technology are described. Influences of photol ithography and etching on dimensional accuracy and resolution are given and some consequences on design rules are shown