The characteristics of hole trapping in HfO2∕SiO2 gate dielectrics with TiN gate electrode

Lu, Wen Tai; Lin, Po Ching; Huang, Tiao‐Yuan; Chien, Chao–Hsin; Yang, Ming; Huang, Ing Jyi; Lehnen, P.

doi:10.1063/1.1808228

Cited by 44 publications

(26 citation statements)

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“…For the device being in strong accumulation during erase operation, this threshold voltage shift being opposed to the ferroelectric influence can only be explained by hole injection from the substrate or electron detrapping that extends into the bulk of the Si : HfO 2 film with increasing time and voltage. Similar observation for TiN/HfO 2 /SiO 2 /p-Si gate stacks has already been made by Lu et al who claimed hole injection from the substrate to be the dominant reason for threshold voltage instabilities at negative voltage stress [11].…”

Section: Resultssupporting

confidence: 59%

Nanosecond Polarization Switching and Long Retention in a Novel MFIS-FET Based on Ferroelectric $\hbox{HfO}_{2}$

Müller

Böscke²,

Schröder

et al. 2012

IEEE Electron Device Lett.

169

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We report the fabrication of completely CMOScompatible ferroelectric field-effect transistors (FETs) by stabilization of a ferroelectric phase in 10-nm-thin Si : HfO 2 . The program and erase operation of this metal-ferroelectric-insulatorsilicon FET (MFIS) with poly-Si/TiN/Si : HfO 2 /SiO 2 /Si gate stack is compared to the transient switching behavior of a TiN-based metal-ferroelectric-metal (MFM) capacitor. Polarization reversal in the MFM capacitor follows a characteristic time and field dependence for ferroelectric domain switching, leading to a higher switching speed with increasing applied field. Similar observations were made for the material when implemented into an MFIS structure. Nonvolatile switching was observed down to 20-ns pulsewidth, yielding a memory window (MW) of 1.2 V. Further increase in gate bias or pulsewidth led to charge injection and degradation of the MW. Retention measurements for up to 10 6 s suggest a retention of more than ten years. Index Terms-Hafnium oxide, metal-ferroelectric-insulatorsemiconductor (MFIS) FET, nonvolatile memory.

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Section: Resultssupporting

confidence: 59%

Nanosecond Polarization Switching and Long Retention in a Novel MFIS-FET Based on Ferroelectric $\hbox{HfO}_{2}$

Müller

Böscke²,

Schröder

et al. 2012

IEEE Electron Device Lett.

169

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“…Mechanism of charge carrier generation.-The origin of positive oxide charge in a hafnium-based gate stack remains controversial between trapping of holes 11,12,26,27 and protons. [3][4][5] The above …”

Section: H662mentioning

confidence: 99%

Charge Trapping Related Degradation of Thin HfAlO∕SiO[sub 2] Gate Dielectric Stack during Constant-Voltage Stress

Samanta

Cheng

Lee

2009

J. Electrochem. Soc.

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Charge carrier generation/trapping and the related degradation of a thin HfAlO/SiO 2 stack in n-type metal-oxide-semiconductor capacitors have been investigated under constant gate voltage stress. The results show that dielectric degradation is a composite effect of neutral trap creation, surface state generation at the Si/SiO 2 interface, and positive charge trapping in the bulk. The neutral traps created during stress are homogeneously distributed across the oxide following Poisson's random statistics. A significant amount of border-trapped charges was observed in both as-deposited and poststressed devices. The kinetics of generation of both oxide-trapped positive charges and interface trapped charges are found to be similar. Both these defects are possibly created by the hydrogen-related species. We demonstrate that compared to HfO 2 devices, HfAlO devices with an equal equivalent oxide thickness ͑EOT͒ show better performances in memory and logic applications. On the contrary, at a given stress voltage, the threshold voltage degradation ⌬V T and stress-induced leakage current degradation in HfAlO samples are larger, indicating a shorter device lifetime compared to the HfO 2 samples of the same EOT.Scaling down the conventional silicon dioxide ͑SiO 2 ͒ film thickness below ϳ2 nm in complementary metal oxide semiconductor ͑CMOS͒ devices leads to excessive leakage current due to the direct tunneling of electrons between the electrodes and device reliability problems. To provide sufficient gate control with reduced gate leakage current, alternative high-dielectrics having a permittivity higher than SiO 2 are being extensively investigated for future generation CMOS devices. 1-17 Among the various high-dielectrics being studied, hafnium oxide ͑HfO 2 ͒ has emerged as the most promising candidate due to its relatively high dielectric constant ͑ ϳ 22͒, large bandgap ͑ ϳ 5.25 eV͒, large conduction-and valence-band offsets, and compatibility with the polysilicon gate process. 2,7,17 However, the major drawback of HfO 2 is that pure as-deposited amorphous HfO 2 crystallizes 6,7 at 400-450°C, resulting in a large leakage current and the paths for oxygen or dopant diffusion in the dielectric via grain boundaries, threshold voltage instability, and defect generation. 7,8 Recently, Zhu et al. 6 showed that alloying of HfO 2 and Al 2 O 3 increases the crystallization temperature up to 1000°C compatible with the thermal budget in standard CMOS process. In the past few years, considerable progress has been made in understanding the effect of aluminum inclusion on electrical and material properties of hafnium aluminate ͑HfAlO͒ films. 6-10 However, little work 11,12 has been done in assessing the reliability of HfAlO films with a tantalum nitride ͑TaN͒ gate. We therefore attempt to investigate charge-carrier generation/trapping in HfAlO dielectrics during constant voltage stress ͑CVS͒ to gain better physical insights into the generation mechanism of oxide charges. ExperimentalFollowing the standard RCA cleaning process, ͑100͒-or...

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“…As expected, the resultant ⌬V th was negative and its magnitude decreased with decreasing stress voltage when ͉V g ͉ Ͼ 2.5 V. This result has been well known coming from the hole trapping in the gate stack. 16 However, the tendency was not monotonic when we kept going on lowering the stress voltage. As ͉V g ͉ Ͻ 2.5 V, we clearly observed that the sign of a͒ ⌬V th changed, indicating that the type of the net trapped charge in the dielectrics has changed from hole to electron and the degradation became much worse with further deceasing stress voltage.…”

mentioning

confidence: 97%

“…They can also get trapped because there are usually plentiful hole traps existing inside the high-dielectrics. 16 Therefore, the resultant ⌬V th was negative. On the contrary, the hole injection is significantly suppressed by the presence of the interfacial layer as the stress voltage becomes smaller and then the effect of trapped electron will gradually prevail over that of trapped hole.…”

mentioning

confidence: 97%

Anomalous negative bias temperature instability behavior in p-channel metal-oxide-semiconductor field-effect transistors with HfSiON∕SiO2 gate stack

Chen

Chien

Lou

2007

Applied Physics Letters

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Articles you may be interested inInvestigation of extra traps measured by charge pumping technique in high voltage zone in p-channel metaloxide-semiconductor field-effect transistors with HfO2/metal gate stacks Appl. Phys. Lett. 102, 012106 (2013); 10.1063/1.4773914 Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 102, 012103 (2013); 10.1063/1.4773479 Analysis of anomalous traps measured by charge pumping technique in HfO2/metal gate n-channel metal-oxidesemiconductor field-effect transistors Analysis of an anomalous hump in gate current after dynamic negative bias stress in HfxZr1-xO2/metal gate pchannel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 101, 052105 (2012); 10.1063/1.4739525Characterization of fast charge trapping in bias temperature instability in metal-oxide-semiconductor field effect transistor with high dielectric constant

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The characteristics of hole trapping in HfO2∕SiO2 gate dielectrics with TiN gate electrode

Cited by 44 publications

References 5 publications

Nanosecond Polarization Switching and Long Retention in a Novel MFIS-FET Based on Ferroelectric $\hbox{HfO}_{2}$

Nanosecond Polarization Switching and Long Retention in a Novel MFIS-FET Based on Ferroelectric $\hbox{HfO}_{2}$

Charge Trapping Related Degradation of Thin HfAlO∕SiO[sub 2] Gate Dielectric Stack during Constant-Voltage Stress

Anomalous negative bias temperature instability behavior in p-channel metal-oxide-semiconductor field-effect transistors with HfSiON∕SiO2 gate stack

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