The circuit and physical design of the POWER4 microprocessor

Warnock, J.; Keaty, J.; Petrovick, John G.; Clabes, Joachim; Kircher, C. J.; Krauter, B.; Restle, P.J.; Zoric, B.; Anderson, C.J.

doi:10.1147/rd.461.0027

Cited by 94 publications

(47 citation statements)

References 27 publications

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“…Nature has an important advantage over electronic circuits because components are connected by wires in threedimensional (3D) space, whereas even the most advanced VLSI (very large scale integration) microprocessor chips use a small number of layers of planar wiring. [A recently produced chip with 174 million transistors has seven layers (3).] Does 3D wiring explain why the volume fraction of wiring in the brain (40 to 60%; see below) is lower than in chips (up to 90%)?…”

Section: Geometrical and Biophysical Constraints On Wiringmentioning

confidence: 99%

Communication in Neuronal Networks

Laughlin

Sejnowski

2003

Science

849

644

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Brains perform with remarkable efficiency, are capable of prodigious computation, and are marvels of communication. We are beginning to understand some of the geometric, biophysical, and energy constraints that have governed the evolution of cortical networks. To operate efficiently within these constraints, nature has optimized the structure and function of cortical networks with design principles similar to those used in electronic networks. The brain also exploits the adaptability of biological systems to reconfigure in response to changing needs.Neuronal networks have been extensively studied as computational systems, but they also serve as communications networks in transferring large amounts of information between brain areas. Recent work suggests that their structure and function are governed by basic principles of resource allocation and constraint minimization, and that some of these principles are shared with human-made electronic devices and communications networks. The discovery that neuronal networks follow simple design rules resembling those found in other networks is striking because nervous systems have many unique properties.To generate complicated patterns of behavior, nervous systems have evolved prodigious abilities to process information. Evolution has made use of the rich molecular repertoire, versatility, and adaptability of cells. Neurons can receive and deliver signals at up to 10 5 synapses and can combine and process synaptic inputs, both linearly and nonlinearly, to implement a rich repertoire of operations that process information (1). Neurons can also establish and change their connections and vary their signaling properties according to a variety of rules. Because many of these changes are driven by spatial and temporal patterns of neural signals, neuronal networks can adapt to circumstances, self-assemble, autocalibrate, and store information by changing their properties according to experience.The simple design rules improve efficiency by reducing (and in some cases minimizing) the resources required to implement a given task. It should come as no surprise that brains have evolved to operate efficiently. Economy and efficiency are guiding principles in physiology that explain, for example, the way in which the lungs, the circulation, and the mitochondria are matched and co-regulated to supply energy to muscles (2). To identify and explain efficient design, it is necessary to derive and apply the structural and physicochemical relationships that connect resource use to performance. We consider first a number of studies of the geometrical constraints on packing and wiring that show that the brain is organized to reduce wiring costs. We then examine a constraint that impinges on all aspects of neural function but has only recently become apparent-energy consumption. Next we look at energy-efficient neural codes that reduce signal traffic by exploiting the relationships that govern the representational

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Section: Geometrical and Biophysical Constraints On Wiringmentioning

confidence: 99%

Communication in Neuronal Networks

Laughlin

Sejnowski

2003

Science

849

644

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“…Specialized circuits mitigate the skew problem [6], [7], but are difficult to migrate to new technology nodes or new products. In some cases, e.g.…”

Section: Conventional Vlsi Clock Distributionmentioning

confidence: 99%

GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling

Prodanov¹,

Banu²

2006

IEEE Custom Integrated Circuits Conference 2006

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Abstract-We introduce a serial passive clock distribution technique allowing efficient and accurate skew removal at any arbitrary clock drop point. The passive transmission medium may be on-chip electrical transmission lines built in current IC technology or possible optical wave-guides in future developments. The proposed technique is naturally insensitive to practical loses and other non ideal effects and has the capability of covering large chip areas.

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“…Designs with K < 1 are likely to make heavy use of standby modes and other techniques to suppress leakage power which is beyond the scope of this work. A lambda-shaped p(t), peaking at half of the critical delay, is assumed for all further analysis based on static timing analysis results shown in [5,10]. We also performed experiments on a flat path distribution and a sloped distribution where the maximum number of paths occur at the critical delay.…”

Section: Power Optimization Frameworkmentioning

confidence: 99%

Minimizing total power by simultaneous Vdd/Vth assignment

Srivastava

Sylvester

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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-We investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static + dynamic) for the first time. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1V processes. Rules of thumb are developed for optimal Vdd's and Vth's to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the total power savings is significantly greater than previously anticipated. We describe the impact of level conversion delays and highlight the tradeoff between power savings and critical path count.

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The circuit and physical design of the POWER4 microprocessor

Cited by 94 publications

References 27 publications

Communication in Neuronal Networks

Communication in Neuronal Networks

GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling

Minimizing total power by simultaneous Vdd/Vth assignment

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