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The POWER4 chip, functioning in the laboratory at frequencies >1GHz, contains two independent processor cores, a shared L2, an L3 directory and all of the logic needed to form large SMPs. The chip, containing over 170M transistors, is fabricated using a 0.18µm CMOS SOI technology with 7-layer copper metallization. The physical design challenges for this chip are to guarantee functionality of all circuits, meet cycle time goals, check complex ground rules, verify that the transistors implement the VHDL properly, and meet test, power, and clock-distribution requirements on an aggressive schedule with a design team at multiple geographically-separated sites.Each POWER4 core [1] is an out-of-order superscalar design containing an instruction fetch unit with its 64kB L1 instruction cache, an instruction decode unit, two fixed-point and two floating-point execution units, dual load store execution units with a dual-ported 32kB L1 data cache, a branch execution unit, an execution unit to perform logical operations on the condition register, and a sequencing unit to manage instructions in flight. Instructions can be issued to each execution unit every cycle. Up to 8 data and 3 instruction cache misses are supported. In excess of 200 instructions can be in various stages of execution. The two cores share an 8-way set-associative unified L2 organized as 3 independent cache controllers. In aggregate, 12 outstanding L2 misses can be supported by the L2. Figure 15.2.1 shows an 8-way module, with 4 POWER4 chips, that is used as a system building block. A photo of the actual multi-chip module is shown in Figure 15.2.2. All logic necessary to communicate between POWER4 chips is contained on the chip. Multiple modules can be interconnected to form larger SMP systems. POWER4 to POWER4 buses on and off module operate at half the processor speed. Buses to and from an off-chip L3 and memory operate at one-third the processor speed. Figure 15.2.3 lists the number of objects that are placed on the chip. The chip, with 2208 signal I/O C4s and over 5500 total C4s including power and ground, supports greater than 1Tb/s peak bandwidth.The chip physical design is built on a hierarchy of transistors, macros, units, microprocessor cores and chip. Three types of macros are employed: custom, SRAM and synthesized. During the high-level design phase, the macros, units, core and chip are all assigned contracts for timing, area, shape, wiring tracks and I/O. Timing and physical design of the chip are done concurrently on all levels of the hierarchy. All major buses are routed early in the design. Figure 15.2.4 shows the floorplanned buses. As the design progresses contracts are modified to reflect the actual design. Significant design constraints include maintaining a slew rate of <300ps on all transitions, with a wire signal delay of approximately 100ps/mm. These constraints require more than 70k buffers/inverters to be inserted. In the final months of the design, turn-around-time from entering design changes to a chip level timing run is <1 day. ...

Solid polymer electrolytes are an emerging technology in electrochemistry driven by their use in energy applications such as fuel cells, electrolyzers, and solid-state batteries. Compared to traditional liquid electrolytes, solid polymer electrolytes provide safer, cheaper, and potentially improved device performance. However, there is a lack of standard experimental methods for studying solid electrolytes. Microelectrodes have inherent benefits capable of filling this experimental gap due primarily to their integration into model electrochemical cells with solid electrolytes that represent complex interfaces, enabling additional insight into reaction processes. In this tutorial review, we explore the use of microelectrodes to study solid polymer electrolytes, beginning with a brief history of the field including common experimental cell designs and their benefits and drawbacks. Methods of evaluating essential kinetic and mass-transport parameters are then examined. In addition, the key studies of the past 30 years utilizing microelectrode cells and solid polymer electrolytes are summarized, with important results highlighted and compared. Finally, future studies of solid polymer electrolytes with microelectrodes and potential new avenues of research are commented on.