The core clock system on the next-generation ltaniumlm microprocessor

Anderson, Ferd; Wells, J.; Berta, E.Z.

doi:10.1109/isscc.2002.992166

Cited by 13 publications

(9 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The energy ( ) needed to create a voltage swing with capacitance when using a detector with external quantum efficiency is: (1) where is the energy in one photon and the elementary charge. Since two pulses are necessary every cycle, the minimum averaged optical power will be: (2) where is the DC-responsivity (A/W) of the detector as generally defined in the literature [14].…”

Section: Receiver-less Clock Injectionmentioning

confidence: 99%

“…In comparing our model to clock distribution in present microprocessors [1], [4], we note that although H-tree configurations are increasingly more widely adopted, they are generally not as uniformly constructed as in our model. Firstly, the inverters from sets of levels in our model are in practice grouped together, to give roughly three total stages of larger buffers (for the Itanium microprocessor the three buffer stages are called the Primary Driver, Second Level Clock Buffers (SLCB) and Gaters).…”

Section: Modeling Of An Optical Clock Distribution Treementioning

confidence: 99%

“…However, lumping sets of levels to produce larger buffers would not significantly alter the results of the modeling presented here. 1 In fact disregarding wire effects, the three buffer stages approach is exactly the same as our constant FO-4 approach, because each large buffer is composed of smaller buffers in a FO-4 chain.…”

Section: Modeling Of An Optical Clock Distribution Treementioning

confidence: 99%

“…Clock distribution in current microprocessors involves delivering a sharp noise-free clock to over a hundred thousand static and dynamic latches, which combined, present a capacitive load of several nanofarads. For example, in the Itanium processor [1] a total of 7 nF of capacitance has to be switched with accurate timing every cycle. The power required to charge and discharge this capacitance alone is 23 W. Unfortunately, most circuit design approaches used for correcting the aforementioned shortcomings of wires add to the chip power consumption.…”

mentioning

confidence: 99%

“…Global routes are carefully handcrafted with local shielding to reduce jitter and accurately control impedance. Differential signaling is sometimes necessary to reduce signal coupling [1], and extensive modeling is done to minimize skew, jitter and inductive effects [2].…”

mentioning

confidence: 99%

See 4 more Smart Citations

Receiver-less optical clock injection for clock distribution networks

Debaes

Bhatnagar

Agarwal

et al. 2003

IEEE J. Select. Topics Quantum Electron.

View full text Add to dashboard Cite

Abstract-We present a new technique of injecting clocks optically onto CMOS chips without the use of a receiver amplifier. We discuss the benefits of such a direct approach and present proof-ofprinciple experiments of the technique. We analytically compare a receiver-less optical clock distribution and an electrical clock distribution in a fan-out-of-four clock tree to evaluate the timing and power benefits of the optical approach for present microprocessors. We also compare receiver-less direct injection of optical clocks to trans-impedance receiver based injection within the same distribution framework.

show abstract

Section: Receiver-less Clock Injectionmentioning

confidence: 99%

Section: Modeling Of An Optical Clock Distribution Treementioning

confidence: 99%

Section: Modeling Of An Optical Clock Distribution Treementioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

Receiver-less optical clock injection for clock distribution networks

Debaes

Bhatnagar

Agarwal

et al. 2003

IEEE J. Select. Topics Quantum Electron.

View full text Add to dashboard Cite

show abstract

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

Pal,

Upadhyaya,

Majumder

et al. 2024

Eng. Res. Express

View full text Add to dashboard Cite

In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

show abstract