2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers 2014
DOI: 10.1109/vlsit.2014.6894375
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The demonstration of colossal magneto-capacitance and “negative” capacitance effect with the promising characteristics of Jg-EOT and transistor's performance on Ge (100) n-FETs by the novel magnetic gate stack scheme design

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Cited by 3 publications
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“…In the BFO/BTO ML system, the complex BFO and BTO diffraction patterns in the split conditions from Condition A (ML-A) to Condition C (ML-C) are shown in Figure 2c. It can be observed that all prepared ML multi-ferroic BFO/BTO samples were polycrystalline in nature with a rhombohedral distortion for BFO and a tetragonal distortion for BTO [4], respectively.…”
Section: Resultsmentioning
confidence: 99%
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“…In the BFO/BTO ML system, the complex BFO and BTO diffraction patterns in the split conditions from Condition A (ML-A) to Condition C (ML-C) are shown in Figure 2c. It can be observed that all prepared ML multi-ferroic BFO/BTO samples were polycrystalline in nature with a rhombohedral distortion for BFO and a tetragonal distortion for BTO [4], respectively.…”
Section: Resultsmentioning
confidence: 99%
“…With the growth and the recent development of magnetic sensors [1,2], magnetic electric devices [3,4], and logic Magneto-Electric Spin-Orbit (MESO) devices [5,6], a multiferroic material with a good ferroelectricity, low tunneling current (J g ), and strong magnetoelectric effect is needed urgently. In the past, we investigated the material properties of pure ferroelectric BaTiO 3 (BTO) and pure multi-ferroic BiFeO 3 (BFO) thin films separately [7,8].…”
Section: Introductionmentioning
confidence: 99%
“…Post deposition annealing (1150 • C, 10 minutes) was used on the BaTiO 3 HK layer to form the tetragonal phase, which has the higher intrinsic K value (∼178) and the better sensitivity for the K value improvement with the implement of the magnetic field. 5,9 Following the deposition of the HK/MG layers, lithography process and Cl plasma dry etching process were employed to define and pattern the gate stack region (channel length L g = 10 µm). Wafers were then implanted with phosphorus (P + , 18 KeV, and 4 × 10 15 cm −2 ) ions to form the self-aligned n + S/D regions.…”
Section: Methodsmentioning
confidence: 99%