The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

Xanthopoulos, Thucydides; Bailey, Diana M.; Gangwar, Ankita; Gowan, M.K.; Jain, Ankesh; Prewitt, B.K.

doi:10.1109/isscc.2001.912693

Cited by 51 publications

(35 citation statements)

References 2 publications

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“…The complexity is further increased in 3-D ICs as sequential elements belonging to the same clock domain (i.e., synchronized by the same clock signal) can be located on different planes. Another important issue in the design of clock distribution networks is low power consumption, since the clock network dissipates a significant portion of the total power consumed by a synchronous circuit [55]. This demand is stricter for 3-D ICs due to the increased power density and related thermal limitations.…”

Section: Synchronization In 3-d Circuitsmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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Section: Synchronization In 3-d Circuitsmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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“…The complexity is further increased in 3-D ICs as sequential elements belonging to the same clock domain (i.e., synchronized by the same clock signal) can be located on different planes. Another important issue in the design of clock distribution networks is low power consumption, since the clock network dissipates a significant portion of the total power consumed by a synchronous circuit [101], [102]. This demand is stricter for 3-D ICs due to the increased power density and related thermal limitations.…”

Section: Synchronization In 3-d Circuitsmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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“…The Alpha processor [12] illustrates the need for flexible clocking schemes in order to enable core reuse in systemon-chip (SOC) designs. The entire chip is partitioned into 11 clock domains, where one domain is a migration of a processor core from an older design.…”

Section: Mixed Synchronous=asynchronous Solutionsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

Cited by 51 publications

References 2 publications

Physical Design Issues in 3-D Integrated Technologies

Physical Design Issues in 3-D Integrated Technologies

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Asynchronous on-chip networks

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