The Design of Storage System for Digital Airborne Camera Based on SOPC

Wu, Yakun; Duan, Xiaohui; Lian, Zhouhui; Zhao, Shihu; Yan, Lei

doi:10.1109/cisp.2008.599

Cited by 7 publications

(4 citation statements)

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“…And a 32 MB with 32 bit SDRAM is set as cache storage to establish balance between the irresistible data flow, with almost 58 MB/s from CCD I/O port, and the lower tested access flow, with 55.98 MB/s to IDE interface hard disk. Two 512 KB with 16 bits SRAM chips (SRAMI and SRAM2) are alternately used as frame memories for VGA Displayer [5]. A 1 MB with 16 bit FLASH chip and a 512 KB with 16 bit SRAM are NIOS memories.…”

Section: IImentioning

confidence: 99%

Digital storage system for newly twice-imaging airborne camera device

Yan

Duan

et al. 2008

2008 2nd International Symposium on Systems and Control in Aerospace and Astronautics

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Abundant real-time image data are generated during aerial survey period. Through design of a digital storage system, data from a newly twice-imaging airborne camera device are timely and faultlessly stored in an IDE (Integrated Drive Electronics) hard disk. The system has data acquisition, storage and preview functions. Particularly, it receives data burst of nearly 58 MB/s and stores them within 2 seconds. And then, personal computer reads them out from hard disk through USB interface for subsequent processing, analyzing and serving.

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Section: IImentioning

confidence: 99%

Digital storage system for newly twice-imaging airborne camera device

Yan

Duan

et al. 2008

2008 2nd International Symposium on Systems and Control in Aerospace and Astronautics

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“…The image is controlled by varying the parameters of the LCD touch panel where the image is displayed after getting processed through FPGA device. The FPGA device has the flexibility to do different complexity process such as integrations of the peripherals and running image processing algorithms without incurring any extra cost of the hardware [1][2][3]. It's worth knowing that the algorithms used with the software languages such as C/C++ is slower than that of the hardware image processing algorithms.…”

Section: Introductionmentioning

confidence: 99%

Implementation of FPGA Based Digital Camera System Controlled from an LCD Touch Panel

Ummaruddin

Phade

Gandhe

et al. 2015

2015 International Conference on Computing Communication Control and Automation

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Today's Field Programmable Gate Arrays (FPGA's) are in use to implement high performance image processing systems. In this paper it is used in implementation of a FPGA based digital camera system for image capturing and real time image processing. Image captured by a Complementary Metal Oxide Semiconductor (CMOS) camera's image sensor are initially stored in the FPGA device memory and then they are displayed on the Liquid Crystal Display (LCD) digital touch panel. The main goal of this proposed design implementation architecture is to implement and test advanced complex image processing algorithm. The device also supports the control of the Complementary Metal Oxide Semiconductor (CMOS) image sensor through the control of the Liquid Crystal Display LCD digital touch panel. Further the FPGA device has the ability to communicate with a Personal Computer (PC) through an interfaced Joint Test Automatic Generation (JTAG) for storing the images on to it and further processing. The structural element of this proposed architecture was chosen to be implemented on ALTERA's DE2 FPGA device.

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“…For example, in [2] a soft processor is used to implement some subsystems of the robot's control system, while time-critical components are performed in hardware. Other examples of this kind of use include [3] and [4].…”

Section: Introductionmentioning

confidence: 99%

The supersmall soft processor

Robinson

Vafaee

Scobbie

et al. 2010

2010 VI Southern Programmable Logic Conference (SPL)

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Soft processors have become an increasingly common component of systems that use Field-Programmable Gate Arrays (FPGAs), and are used to implement a wide variety of control and data processing functionality. Often, some additional functionality needs to be added to a system when there is very little space left on the physical device. This functionality may not be performance critical, and so could be implemented on a slow soft processor. For this reason it may be useful to have a processor that is as small as possible yet similar to other commonly-used processors. This paper describes the design, implementation and release of a 32-bit soft processor based on the MIPS-I instruction set and optimized for minimal use of FPGA resources. The 'supersmall' soft processor is as much as 2.2 times smaller than Altera's Nios II/e (the smallest of their 3 processors) yet only a factor of 10 times slower.

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The Design of Storage System for Digital Airborne Camera Based on SOPC

Cited by 7 publications

References 0 publications

Digital storage system for newly twice-imaging airborne camera device

Digital storage system for newly twice-imaging airborne camera device

Implementation of FPGA Based Digital Camera System Controlled from an LCD Touch Panel

The supersmall soft processor

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