The detection of defects in a niobium tri-layer process

Joseph, Arun; Heuvelmans, S.; Gerritsma, G.J.; Kerkhoff, Hans G.

doi:10.1109/tasc.2003.813654

Cited by 6 publications

(7 citation statements)

References 7 publications

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“…As a result of our earlier research on structural defects in the JeSEF RSFQ process [5], a test chip has been realized for a detailed process analysis. Two types of structure were designed: one set for low-temperature (LT) 4 K testing and the other for room-temperature (RT) 294 K testing.…”

Section: Test Structures and Defect Analysismentioning

confidence: 99%

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Design for the testability of superconductor electronics

Joseph

Kerkhoff

2003

Supercond. Sci. Technol.

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Advances in the electronics industry require ultra high-speed components nowadays. Superconductor electronics (SCE) is emerging as a technology for solutions in high-end applications in computing and communication. As the complexity of the system increases, testing becomes complex and, if not properly addressed, the system becomes non-testable. Hence, complex systems should be designed with testability in mind. The design-for-test structures should be able to detect the faults in the system under study. Controllability and observability are the key features for design for testability (DfT). A system-level study was carried out to verify the feasibility of DfT in SCE. In this paper, we illustrate at circuit level how this can be realized in SCE to monitor single-flux-quantum pulses. As a part of the research we have developed test structures to detect structural defects in SCE devices. We also present the details of the test results of those structures in this paper. This proves that we are able to detect possible random defects and provide defect statistics for a matured fabrication process.

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Section: Test Structures and Defect Analysismentioning

confidence: 99%

“…We have developed special test structures to be realized along with the integrated circuits (ICs) for the Jena Superconductive Electronics Foundry (JeSEF) niobium (Nb) process [4,5]. These test structures were developed as a part of our defect-oriented testing (DOT) approach on SCE [6].…”

Section: Introductionmentioning

confidence: 99%

Design for the testability of superconductor electronics

Joseph

Kerkhoff

2003

Supercond. Sci. Technol.

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“…As a result of our earlier research on structural defects in the JeSEF RSFQ process [4], a test chip has been realised for a detailed process analysis. Two types of structures were designed, one set for low temperature (LT), 4 K testing and the other for room temperature (RT), 294 K testing.…”

Section: Figure 7 Output Of the Monitor Connected To One Of The Inpumentioning

confidence: 99%

“…A model has been developed that has helped to create a method for detecting and pinpointing possible junction defects down to a chain of 20 JJs. The detection method has been developed to reduce the number of thermal cycles needed, thus reducing test cost and test time [4].…”

Section: Isolation Defectsmentioning

confidence: 99%

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Testability Issues in Superconductor Electronics

Kerkhoff¹,

Joseph²

Second IEEE International Workshop on Electronic Design, Test and Applications

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An emerging technology for solutions in high-end applications in computing and telecommunication is Superconductor Electronics. A system-level study has been carried out to verify the feasibility of DfT in superconductor electronics. In this paper, we present how this can be realized to monitor so-called single-flux quantum pulses. As a part of our research, test structures have been developed to detect structural defects in this technology. We also show detailed test results of those structures. It proves that it is possible to detect possible random defects and provide defect statistics for the Niobium-based fabrication process.

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