The Development and the Integration of the 5 µm to 1 µm Half Pitches Wafer Level Cu Redistribution Layers

Ma, Mike; Chen, Stephen; Wu, Po-I; Huang, Ann; Lu, Chi-Jen; Chen, Alex; Liu, Cheng-Hsiang; Peng, Shih-Liang

doi:10.1109/ectc.2016.156

Cited by 12 publications

(2 citation statements)

References 2 publications

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“…Figure 31 shows the cross section of a FOWLP with hybrid RDLs published by SPIL in Ref. [109]. For other hybrid-RDLs, see Refs.…”

Section: Hybrid-redistribution Layers (First Inorganic Redistributionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…Figure 31 shows the cross section of a FOWLP with hybrid RDLs published by SPIL in Ref. [109]. For other hybrid-RDLs, see Refs.…”

Section: Hybrid-redistribution Layers (First Inorganic Redistributionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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“…The damascene process is a wiring process that relies on the CMP to remove extra material. It can effectively improve the surface flatness and reduce the total thickness variation in multilayer wiring, making it possible to generate a higher density of lines using lithography [28]. Thus, the effectiveness of the CMP method could be verified in the damascene process.…”

Section: Introductionmentioning

confidence: 99%

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

Chen¹,

Han²,

Xiao³

et al. 2022

Flex. Print. Electron.

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With the rapid development of flexible electronics, an increasing number of microfabrication strategies originating from the Si-based integrated circuits field have been explored on organic materials. Parylene C, a polymer, has been widely used in the microelectromechanical systems (MEMS) field because of its outstanding fabrication merits, such as room-temperature processability, conformal coating, and precise thin film deposition capability with the thickness tunable from 1 nm to 100 μm. As a good dielectric material, the Parylene C is also suitable for interlayer dielectrics (ILD) in flexible electronics. This study develops an optimized chemical mechanical polishing (CMP) technique of Parylene C for high-density redistribution wiring in high-performance flexible electronics. The roughness of the Parylene C surface after CMP was as low as 14.3±1.5 Å. The problems of slurry pollution and mechanical failure of the Parylene film that degrade the dielectric performance of the Parylene C could be avoided by taking the optimized CMP method. The multi-material structure constructed by Parylene C, Silicon and electroplated Copper was prepared and polished using the optimized CMP process. Additionally, a flexible wiring sample has been successfully patterned by the Damascene process through the optimized CMP process. In this sample, both the distance between each wire and the wire width were as small as 5 μm.The optimized Parylene C CMP process is easy-to-realize, highly efficient, low cost, and with minor defects; it provides a promising way to achieve high-density interconnection in high-performance flexible electronic devices.

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Fan-Out Wafer/Panel-Level Packaging for Heterogeneous Integrations

Lau

2019

Heterogeneous Integrations

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The Development and the Integration of the 5 µm to 1 µm Half Pitches Wafer Level Cu Redistribution Layers

Cited by 12 publications

References 2 publications

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

Fan-Out Wafer/Panel-Level Packaging for Heterogeneous Integrations

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