The DIMM tree architecture: A high bandwidth and scalable memory system

Therdsteerasukdi, Kanit; Byun, Gyung-Su; Ir, Jeremy; Reinman, Glenn; Cong, Jason; Chang, Mau-Chung Frank

doi:10.1109/iccd.2011.6081428

Cited by 18 publications

(45 citation statements)

References 13 publications

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“…In addition, these models are validated with prototypes for different transmission lines [19][24], while following ITRS [25]. We determine RF-interconnection power as in [5]: using McPAT [6] tool at different frequencies to determine FE/TE power components and RFinterconnection power modeling as in [4].…”

Section: A Methodologymentioning

confidence: 99%

“…RFiof is designed to scale to 32 RFMCs and 345.6 GB/s, using 10.8GB/s ranks; however given its lower number of pins and the adoption of a conventional RF-interface (FR-board as in DIMM Tree [4]), this technology has the potentiallity to be scaled to use 64 RFMCs and ranks of 17.2 GB/s and likely achieve the bandwidth of 1024GB/s (and total width of 4096 bits), which is an expressive bandwidth level. …”

Section: A Backgroundmentioning

confidence: 99%

“…As a consequence, Corona [3] is able to scale to 64 optical-MCs while DIMM Tree [4] up to 64 RFMCs (RFbased memory controllers). In previous advanced systems, total memory width is estimated about 4096 bits when interfaced to simple double data rate (DDR) memories.…”

Section: Introductionmentioning

confidence: 99%

“…These advanced interfaces rely on optical-and radio-frequency (RF) technologies, which allow them to use fewer I/O pins, allowing further degrees of MC scalability. For example, Corona [3] utilizes only two optical pins and DIMM Tree employs 39 RFpins [4], which are significantly less than 240 I/O pins present in traditional DDR families.…”

Section: Introductionmentioning

confidence: 99%

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Implications of shallower memory controller transaction queues in scalable memory systems

Marino¹,

2015

J Supercomput

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Scalable memory systems provide scalable bandwidth to the core growth demands in multicores and embedded systems processors. In these systems, as memory controllers (MCs) are scaled, memory traffic per MC is reduced, so transaction queues become shallower. As a consequence, there is an opportunity to explore transaction queue utilization and its impact on energy utilization. In this paper, we propose to evaluate the performance and energy-per-bit impact when reducing transaction queue sizes along with the MCs of these systems. Experimental results show that reducing 50% on the number of entries, bandwidth and energy-per-bit levels are not affected, whilst reducing aggressively of about 90%, bandwidth is similarly reduced while causing significantly higher energy-per-bit utilization.

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Section: A Methodologymentioning

confidence: 99%

Section: A Backgroundmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Implications of shallower memory controller transaction queues in scalable memory systems

Marino¹,

2015

J Supercomput

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“…DIMM tree architecture was proposed to overcome the drawbacks of the traditional DIMM interface methods, and to implement the many-DIMM system [3]. This tree architecture uses a special type of DIMMs called tree DIMMs (T-DIMMs) connected by a tree topology [4], as shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

A T-DIMM ID Based Command Routing Method for the DIMM Tree Architecture

Kim

Moon

2015

IJCA

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Exploiting dynamic transaction queue size in scalable memory systems

Marino

Weng

2017

Soft Comput

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In order to increase parallelism via memory width in scalable memory systems, a straightforward approach is to employ larger number of memory controllers (MCs). Nevertheless, a number of researches have pointed out that, even executing bandwidth-bound applications in systems with larger number of MCs, the number of transaction queue entries is under-utilized -namely as shallower transaction queues, which provides an opportunity to power saving. In order to address this challenge, we propose the use of transaction queues with dynamic size that employs the most adequate size, taking into consideration the number of entries utilized while presenting adequate levels of bandwidth and minimizing power. Experimental results show that, while saving up to 75% number of entries, the introduction of dynamic transaction queue mechanism can present savings up to 75% of bandwidth and 20% of rank energy-per-bit reduction compared to systems with 1-2ntries. With such promising results, it can be aimed and incorporated in modelling methodologies directed to the design and evaluation of new generation embedded systems.

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The DIMM tree architecture: A high bandwidth and scalable memory system

Cited by 18 publications

References 13 publications

Implications of shallower memory controller transaction queues in scalable memory systems

Implications of shallower memory controller transaction queues in scalable memory systems

A T-DIMM ID Based Command Routing Method for the DIMM Tree Architecture

Exploiting dynamic transaction queue size in scalable memory systems

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