The Equator MAP-CA/spl trade/ DSP: an end-to-end broadband signal processor/spl trade/ VLIW

A AbstractRecently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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“…As a result, DSPs have been successfully used in a wide range of image processing applications [34][35][36][37][38][39].…”

Section: Digital Signal Processor (Dsp)mentioning

confidence: 99%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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“…Moreover, Equator MAP-CA [34] and Philips TriMedia [35] are media processors allowing SIMD instructions.…”

Section: Commercial Processors With Multimedia Extensionmentioning

confidence: 99%

Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

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“…In comparison, Equator's MAP-CA processor [15] has been reported to only decode MPEG-4 ASP Level 3 in CIF format at 300 MHz [16]. Dedicated implementations, e.g., Sigma Design's EM847× family [17] frequently lack support for features specific to the ASP, such as quarter-pel motion compensation or global motion compensation.…”

Section: Application Example: Mpeg-4 Advanced Simple Profilementioning

confidence: 99%

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

Stolberg

Berekovic

Friebe

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 µm 6LM standard-cell CMOS technology, occupies about 81 mm 2 , and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.

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The Equator MAP-CA/spl trade/ DSP: an end-to-end broadband signal processor/spl trade/ VLIW

Cited by 19 publications

References 28 publications

Efficient reconfigurable architectures for 3D medical image compression

Efficient reconfigurable architectures for 3D medical image compression

Configurable Data Memory for Multimedia Processing

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

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