The FPGA High-Performance Computing Alliance Parallel Toolkit

Baxter, Rob; Booth, Stephen; Bull, Mark; Cawood, Geoff; Perry, James; Parsons, Mark; Simpson, Andrew; Trew, Arthur; McCormick, A.C.; Smart, George; Smart, Rosanna; Cantle, Allan J.; Chamberlain, Roger D.; Genest, G.

doi:10.1109/ahs.2007.104

Cited by 7 publications

(3 citation statements)

References 1 publication

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“…Unlike multi-processor computations, there are no standardized methodologies, interfaces, or tools for multi-FPGA based platforms. Although there were attempts to introduce a multi-FPGA equivalent of OpenMP [27], no uniform approach has been established yet. Considering the variety of applications and architectures (from FPGA-dominated clusters to servers based on hybrid CPU-FPGA chips) as well as diverse temporal granularity, differences in firmware development methodology are understandable.…”

Section: Related Workmentioning

confidence: 99%

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

et al. 2020

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ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, all-in-one VHDL description of variable Processing Elements (PEs) is developed manually. GCC preprocessing is then used to extract only the desired target functionality. A dedicated software instantiates and connects PEs in form of a scalable network, divides it into subsets for chips and generates its HDL description. As a result, individual HDL-coded specification, optimized for certain analysis, is provided for the synthesis tool. Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead. The PE network can be scaled inversely proportional to PEs complexity, in order to efficiently utilize available resources. Moreover, downscaling the problem makes verification during HDL simulations and testing the prototype systems easier.

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Section: Related Workmentioning

confidence: 99%

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

et al. 2020

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“…A line of special purpose development boards based on such FPGAs are also available(e.g. Nallatech and Alpha data) which are particularly suitable for HPC; some of these come with tools which help faster algorithm-to-hardware realization with high-level C-like constructs; Maxwell [1,2], a FPGA parallel computer, is a good example of a system built around such hardware/software ecosystem.…”

Section: Introductionmentioning

confidence: 99%

FPGA Based High Performance Double-Precision Matrix Multiplication

Kumar

Joshi

Patkar

et al. 2010

Int J Parallel Prog

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We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of local-memory and bandwidth for an FPGA implementation are demonstrated and an analysis is presented for the optimal choice of design parameters. The designs, implemented on a Virtex-5 SX240T FPGA, scale gracefully from 1 to 40 processing elements(PEs) with a less than 1% degradation in the design frequency of 373 MHz. With 40 PEs and a design speed of 373 MHz, a sustained performance of 29.8 GFLOPS is possible with a bandwidth requirement of 750 MB/s for design-II and 5.9 GB/s for design-I. This compares favourably with both related art and general purpose CPU implementations.

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“…Linux systems are running independently on each node and communicate through MPI [8]. A custom framework called Parallel Toolkit (PTK) [2] was used as middle-ware between user applications and vendor specific drivers. This toolkit is based on the request-grant model of abstract hardware types to manage FPGA resources and to transfer data.…”

Section: Related Workmentioning

confidence: 99%

Programming framework for clusters with heterogeneous accelerators

Tsoi

Tse

Pietzuch

et al. 2010

SIGARCH Comput. Archit. News

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We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources productively and efficiently. The distributed application is highly modularized to support dynamic system configuration with changing types and number of the accelerators. Multiple layers of communication interface are introduced to reduce the overhead in both control messages and data transfers. Parallelism can be achieved by controlling the accelerators in various schemes through scheduling extension. The framework has been used to support physics simulation and financial application development. We achieve significant performance improvement on a 16-node cluster with FPGA and GPU accelerators.

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The FPGA High-Performance Computing Alliance Parallel Toolkit

Cited by 7 publications

References 1 publication

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

FPGA Based High Performance Double-Precision Matrix Multiplication

Programming framework for clusters with heterogeneous accelerators

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