The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate

Cannon, Ethan H.; KleinOsowski, A.J.; Kanj, Rouwaida; Reinhardt, D.D.; Joshi, Rajiv V.

doi:10.1109/tdmr.2007.912983

Cited by 52 publications

(13 citation statements)

References 12 publications

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“…Effects of variability on error rate in the literature has mostly been addressed through critical charge modeling in different process corners or analytical modeling [4][5][6][7][8][9][10] or through critical charge spread modeling with monte-carlo drawing of transistor parameters [11][12][13][14]. Few alpha experimental results are available in the literature and no neutron data has ever been reported.…”

Section: Introductionmentioning

confidence: 99%

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Gasiot

Glorieux

Uznanski

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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This paper shows alpha and neutron experimental Soft Error Rate characterization of a SRAM test vehicle processed with different process corners in order to emulate the variability encountered in volume production. It allows assessing large variability effects with few samples that are compatible with accelerated SER testing. This allows investigating the effect of variability in mass-production on soft error rate of decananometric technologies. Keywords-Process corner; Soft Error Rate; alpha and neutron experiments;manufacturing process variability; volume productionI.

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Section: Introductionmentioning

confidence: 99%

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Gasiot

Glorieux

Uznanski

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…Particularly, to the best of our knowledge, so far the effects of aging on circuit Soft Error Rate (SER) have been analyzed only in [17,18,19,20,21]. In [17,18], the impact of aging on the critical charge of SRAM cells has been considered, showing that NBTI has a limited impact on the memory cell critical charge, thus on the memory SER. Instead, in [19], it has been analyzed how the SER of some combinational benchmark circuits varies with circuit life time.…”

Section: Introductionmentioning

confidence: 99%

Impact of Bias Temperature Instability on Soft Error Susceptibility

Rossi

Omaña

Metra

et al. 2015

IEEE Trans. VLSI Syst.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , TVLSI-00281-2013 1 Impact of Bias Temperature Instability on Soft Error SusceptibilityAbstract-In this paper we address the issue of analyzing the effects of aging mechanisms on ICs' soft error susceptibility. Particularly, we consider Bias Temperature Instability (BTI), namely Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors, that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the soft error susceptibility of the whole IC. We then propose a time dependent model for soft error susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the IC's lifetime.Index Terms-Aging, bias temperature instability, critical charge, soft error.

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“…However, the impact of the transistor switching delay may lead to an increase in the susceptibility to neutron-induced bit-flip in SRAM memory cells due to its slow answer to signal recovery, as discussed in [3,4]. High-energy neutrons are produced in nuclear cascade showers created by nuclear spallation reactions between cosmic rays (mainly protons) and atmospheric nuclei (nitrogen and oxygen) and reach the ground level.…”

Section: Introductionmentioning

confidence: 99%

“…In consequence, they may present a significant aging effect and must be tolerant to neutron-induced soft errors. Related works have already shown that NBTI can lead to a small increase of the Soft Error Rate (SER) in SRAM cells fabricated in 45 nm CMOS technologies [3,4,6].…”

Section: Introductionmentioning

confidence: 99%

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

Kastensmidt¹,

Tonfat²,

Both³

et al. 2014

Microelectronics Reliability

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International audienceThis work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based Field Programmable Gate Array (FPGA). Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical level for aging, soft error and different voltages in SRAM memory cells was described to investigate by simulation in more details the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode

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The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate

Cited by 52 publications

References 12 publications

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Impact of Bias Temperature Instability on Soft Error Susceptibility

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

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