This paper investigates the effects of fringing field arising out of high-k (dielectric constant) gate insulator on the device performance of a p-channel double-gate junctionless transistor (p-DGJLT). The overall device performance of a p-DGJLT is degraded with such fringing field. This behavior is similar to its n-channel counterpart of similar dimension. The effects of spacers on both sides of high-k gate oxides are also studied for the device performance parameters, namely: drain current (I D ), ON-state current (I ON ), threshold voltage (V T ), subthreshold slope (SS) and drain-induced barrier lowering (DIBL). SS and DIBL are improved for the device in which spacer dielectrics are included. However, V T and I ON are degraded with increase in spacer dielectric constant.Index Terms-Fringing field, p-channel junctionless transistor (JLT), scaling, spacer dielectric, subthreshold slope.