The impact of through silicon via proximity on CMOS device

International audienceThis paper aims at determining thermomechanical stress variations induced by annealed copper filled through-silicon via (TSV) in single crystalline silicon using metal-oxide-semiconductor (MOS) rosette sensors. These eight branches sensors were specifically designed and embedded in a 65-nm CMOS technology test vehicle. An in-house four-point bending tool was employed to calibrate and to extract the six independent piezoresistive coefficients. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on wafer splits. A finite-element approach was also adopted to evaluate numerically the stresses and the expected mobility variations induced by TSV. According to this paper, a large variation of stresses (up to 100 MPa) in the sensor area was estimated, suggesting possible sensor design improvements to better accuracy. A good agreement was obtained between numerical and experimental results, except for the orthoradial component, which was found slightly compressive experimentally. Based on a critical analysis of the experimental-numerical methodology and results detailed in this paper, guidelines are drawn to get better accuracy through the improvement of MOS size and positions as well as recommendations regarding test strategy to overcome process variability. In the longer term, such improvements should lead to the definition of a comprehensive strategy for mechanical stress probing with in situ structures in advanced semiconductor products

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The impact of through silicon via proximity on CMOS device

Cited by 2 publications

References 4 publications

Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

Investigations of Thermomechanical Stress Induced by TSV-Middle (Through-Silicon via) in 3-D ICs by Means of CMOS Sensors and Finite-Element Method

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