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This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO 2 layer effect, zero-stress temperature, single and array vias, through and blind vias, as well as diameter and pitch of vias. From the results of this study, the zero-stress temperature has been successfully determined from experimental data. The KOZs based on the more than 10% change in carrier mobility (or 5% saturated current changes) have been identified by finite element numerical calculations associated with related piezoresistive coefficients. Numerical results of saturated current changes have been validated by good comparisons with experimental data. Based on the detailed analyses using this validated model, the key parameters affecting the KOZs will be presented and discussed in detail.

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